Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Toshifumi Irisawa

Tsutomu Tezuka

Naoharu Sugiyama

Shinichi Takagi

Kensuke Ota

Toshinori Numata

Masumi Saitoh

Atsuhiro Kinoshita

Yoshinori Tsuchiya

Daisuke Matsushita

Kiwamu Sakuma

Junji Koga

Tomoya Kawai

A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.

Semiconductor memory device

A semiconductor device according to an embodiment includes a first region including an oxide semiconductor containing indium (In), gallium (Ga), and zinc (Zn), a second region and a third region between which the first region is disposed, at least one of the second region and the third region having a higher indium (In) concentration than the first region and containing at least one metal element from the group consisting of titanium (Ti), tungsten (W), copper (Cu), zinc (Zn), aluminum (Al), lead (Pb), and tin (Sn), an electrode; and an insulating layer disposed between the first region and the electrode.

Semiconductor device and method for manufacturing the same

A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.

Field effect transistor, integrated circuit element, and method for manufacturing the same

A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a &#x3c;110&#x3e; direction.

Semiconductor device and manufacturing method thereof

In a semiconductor device including a multi-gate MIS transistor having a channel on a plurality of surfaces, a gate electrode is formed on a gate insulating film on side surfaces of an island-like semiconductor layer formed along a given direction on an insulating film, and source/drain electrodes are formed in contact with the semiconductor layer. The semiconductor layer has a plurality of side surfaces along the given direction. All angles formed by adjacent side surfaces are larger than 90&#xb0;. A section perpendicular to the given direction is vertically and horizontally symmetrical.

Semiconductor device including multi-gate metal-insulator-semiconductor (MIS) transistor

A semiconductor device includes an n-channel MIS transistor and a p-channel MIS transistor on a semiconductor layer formed on an insulating layer, in which the channel of the n-channel MIS transistor is formed of a strained Si layer having biaxial tensile strain and the channel of the p-channel MIS transistor is formed of a strained SiGe layer having uniaxial compression strain in the channel length direction.

Semiconductor device and method of manufacturing the same

A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a first gate electrode formed on the first gate insulator and including a compound of a metal M and a first group-IV elements SiGe(0&#x2266;a&#x2266;1), the p-type device including a p-channel region formed on the substrate, p-type source and drain regions formed opposite to each other interposing the p-channel region therebetween, a second gate insulator formed on the p-channel region, and a second gate electrode formed on the second gate insulator, and including a compound of the metal M and a second group-IV element SiGe(0&#x2266;c&#x2266;1, a&#x2260;c).

Growing community of inventors

Tokyo, Japan

Toshifumi Irisawa