Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Device Engineering Co., Ltd.

Toshiaki Nishimoto

Hitoshi Kume

Kazuhiro Komori

Satoshi Meguro

Yoshiaki Kamigaki

Masataka Kato

Tetsuo Adachi

Takashi Kobayashi

Toshiyuki Mine

Nozomu Matsuzaki

Hideaki Yamamoto

Yoshimi Sudou

Toshihiro Tanaka

Osamu Tsuchiya

Takashi Aoyagi

Shogo Kiyota

Toshihisa Tsukada

Tadashi Muto

Toshiko Koizumi

Shoji Shukuri

Norio Suzuki

Kenji Takahashi

Takeshi Wada

Tsutomu Okazaki

Takaaki Hagiwara

Kikuo Kusukawa

Kiyofumi Uchibori

Akemi Miura

Hideo Tobe

A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device

A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements

Semiconductor integrated circuit device having single-element type non-volatile memory elements

Method of manufacturing a semiconductor memory device having a non-volatile memory cell portion with single misfet transistor type memory cells and a peripheral circuit portion with misfets

A simple and easy method for exercising quality control over memory cell inter-layer dielectric film within a short period of time, using a memory array or single memory formed in the scribe area, without stressing nonvolatile semiconductor memory cells and a method of manufacturing a nonvolatile semiconductor memory device; whereby a single nonvolatile memory is formed in an area other than a chip area on a semiconductor wafer and used after completion of a wafer manufacturing process to perform an inter-layer dielectric film quality control process for evaluating the write saturation characteristic, cut out nondefective chips only, and conduct a plastic molding process, achieving an increased yield after chip cutting.

Method of testing and manufacturing nonvolatile semiconductor memory

In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions are formed and active regions L sandwiched between the element separation regions are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.

Semiconductor integrated circuit device

Method of manufacturing a semiconductor memory device having a memory cell portion including MISFETs with a floating gate and a peripheral circuit portion with MISFETs

There was a problem that sharpening of a substrate and localized increase in the thickness of a gate oxide film become more remarkable as the thickness of the gate oxide film is increased to degrade the gate withstand voltage at the surface edge of shallow groove isolation structure. In the present invention, a bird's beak is disposed at the surface edge of a shallow isolation structure GROX11 just below gate electrode POLY11 and in contact with the gate insulation film HOX1 to form the gate insulation film HOX1 previously. This can ensure normal gate withstand voltage of the MOS transistor and favorable device isolation withstand voltage and increased integration degree simultaneously.

Semiconductor device having groove isolation structure and gate oxide films with different thickness

A method of manufacturing a semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions. By this method, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. The first semiconductor region is formed to have a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Carriers stored in the floating gate electrode are transferred between the floating gate electrode and the first semiconductor region by tunneling through the insulating film beneath the floating gate electrode. The method further features the formation of MISFETs of peripheral circuits.

Method of manufacturing a semiconductor device having non-volatile memory cell portion with single transistor type memory cells and peripheral portion with MISFETs

Semiconductor integrated circuit device and manufacturing method thereof

A nonvolatile semiconductor memory device is provided which includes a plurality of memory cells each having a floating gate, wherein a threshold level of each memory cell depends on a value of electric charge in said floating gate of said memory cell, and wherein said threshold level of each memory cell is placed at one of a first area and a second area. A controller is also provided which controls to set each threshold voltage of selected ones of said plurality of memory cells, wherein said controller performs a first setting operation and a verifying operation. The first setting operation shifts threshold voltages of the selected ones of said plurality of memory cells in a direction from said first area to said second area. The verifying operation detects erratic memory cells which have threshold voltages which are on a side of said second area which is opposite of a middle area formed between the first area and the second area.

Semiconductor nonvolatile memory apparatus and computer system using the same

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Higashimurayama, Japan

Toshiaki Nishimoto