Sharp Kabushiki Kaisha Corporation

Toshiaki Kinosada

John Kevin Twynam

Motoji Yagura

Hiroya Sato

Toshiyuki Shinozaki

Koken Yoshikawa

Katsuhiko Kishimoto

Masahiro Shiota

Hideyuki Tsuji

Yasuhito Nakagawa

Masanori Kominami

A heterojunction bipolar transistor having a ballast resistance layer between an AlGaAs emitter layer and an emitter electrode, wherein the ballast resistance layer comprises n-Al Ga As, wherein 0<X<1, and a GaAs selective etching layer is provided between the emitter layer and the ballast resistance layer.

Heterojunction bipolar transistor and its manufacturing process

An ohmic electrode structure is produced by developing an In.sub.x Ga.sub.1-x As layer epitaxially on a compound semiconductor (n-Ga As), and providing a barrier layer composed of a tungsten nitride (high melting point metallic nitride) by sputtering. Then, electrode patterning is performed on the top of the tungsten nitride barrier layer by the photo-resist technique. After the process, unnecessary portion of the tungsten nitride barrier layer is removed by the reactive ion etching (RIE). On the top of this a Ti layer, a Pt layer and an Au layer are deposited in layers in that order by the lift-off technique to form a metal layer. Here, molybdenum nitride or titanium nitride may be used in place of tungsten nitride.

Ohmic electrode structure for In.sub.x Ga.sub.1-x As layer

A heterojunction type AlGaAs/GaAs bipolar transistor includes an n-GaAs collector layer, a p.sup.+ -GaAs base layer and an n-Al.sub.x Ga.sub.1-x As emitter layer formed in a stack, and an n-Al.sub.y Ga.sub.1-y As ballast resistance layer formed on the emitter layer. The ballast resistance layer has an Al concentration y in the range of 0&lt;y&lt;0.4, and a resistance higher than that of the emitter layer.

Heterojunction-type bipolar transistor with ballast resistance layer

A hetero-junction bipolar transistor includes: a substrate; a first conductive type collector layer disposed on the substrate; a second conductive type base layer having an external base region; and a first conductive type emitter layer having a bandgap larger than the bandgap of the base layer disposed in this order, wherein the emitter layer includes a first emitter layer, an etching stop layer, and a second emitter layer disposed in this order starting from the substrate side; a base electrode is formed on the etching stop layer or the first emitter layer disposed on the external base region; a region of the first emitter layer on the base layer has a thickness such that the region is substantially depleted at all voltages applied when the transistor is normally operated; the second emitter layer has an electron affinity equal to or smaller than an electron affinity of the first emitter layer; and the etching stop layer has an electron affinity larger than the electron affinity of the first emitter layer, and has a thickness of approximately 3 nm.

Hetero-junction bipolar transistor

The present invention provides a heterojunction bipolar transister includes: a collector layer, a base layer, an emitter layer, a transition layer formed between the base layer and the emitter layer, a collector electrode connected to the collector layer, a base electrode connected to the base layer, and an emitter electrode connected to the emitter layer, wherein the emitter layer and the transition layer are formed of a composition including elements forming the base layer and at least one element different from the elements forming the base layer, a composition of the different element in the transition layer at the emitter side is substantially equal to that of the emitter layer, a composition of the different element in the transition layer at the base side is smaller than that of the emitter side and varies abruptly towards the base layer, and the composition of the transition layer gradingly varies from the base side to the emitter side.

Heterojunction bipolar transistor having low electron and hole

There is provided a method for producing a semiconductor device having a semiconductor layer in which carbon is implanted as an impurity. The method includes the steps of: implanting fluorocarbon ions in a semiconductor layer; and annealing the semiconductor layer to activate the implanted ions.

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Izumi, Japan

Toshiaki Kinosada