Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Mitsubishi Electric Corporation

Other

Ryoden Semiconductor System Engineering Corporation

Toshiaki Iwamatsu

Takashi Ipposhi

Shigenobu Maeda

Yasuo Yamaguchi

Yasuo Inoue

Takuji Matsumoto

Shigeto Maegawa

Yoshiki Yamamoto

Hideki Makiyama

Takaaki Tsunomura

Yuuichi Hirano

Tadashi Nishimura

Shoichi Miyamoto

Hidekazu Oda

Hirofumi Shinohara

Hirotada Kuriyama

Katsuyuki Horita

Masaaki Shinohara

Ryuta Tsuchiya

Hideki Naruoka

Akihiko Furukawa

Kozo Ishikawa

Kyozo Kanamoto

Kazuyuki Sugahara

Kiyoshi Hayashi

Mikio Tsujiuchi

Yuichi Hirano

Yoshiyuki Ishigaki

Takashi Terada

Yasuhiro Kimura

Toshiaki Tsutsumi

Motomu Ukita

Kazuhito Tsutsumi

Hiromasa Yoshimori

Il-Jung Kim

Yoshiko Yoshida

Natsuo Ajika

Tatsuya Kunikiyo

Hirokazu Sayama

Tadaharu Minato

Shiro Hino

Kazunobu Ota

Yukio Maki

Toshiaki Ogawa

Nobuyoshi Hattori

Tomokatsu Watanabe

Hisayuki Nishimura

Yusuke Yamashiro

Mikio Ikeda

Junji Tateishi

Akira Imai

Shinichiro Kimura

Kenji Kawai

Nobuyuki Sugii

Hirotoshi Sato

Jiro Yugami

Takahiro Maruyama

Tatsuhiko Ikeda

Takashi Ishigaki

Masashi Kitazawa

Yusuke Morita

Masaru Takamatsu

Munetaka Noguchi

Akihiro Nakae

Takashi Katakura

Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Semiconductor device

On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

Method of manufacturing semiconductor device

Manufacturing method of semiconductor device including field-effect transistor comprising buried oxide (BOX) film and silicon layer

Semiconductor device and manufacturing method of the same

To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at most 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

Semiconductor device and method for controlling semiconductor device

To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

A silicon carbide semiconductor device includes: an n-type drift layerprovided within an SiC layer; a plurality of p-type well regions; a JFET region JR serving as a part of the drift layersandwiched between the well regions; and a gate insulating filmand a gate electrodeat least covering the JFET region JR. The gate insulating filmand the gate electrodeinclude a different-element-containing regioncontaining an element that is different from elements constituting the gate insulating filmand the gate electrode

Silicon carbide semiconductor device and method for manufacturing same

The technique disclosed in the Description relates to a technique preventing dielectric breakdown while a silicon carbide semiconductor device is OFF, without degrading process throughput or yield. The silicon carbide semiconductor device relating to the technique disclosed in the Description includes a drift layer of a first conductivity type, a threading dislocation provided to penetrate the drift layer, and an electric-field reduction region of a second conductivity type disposed in a position in the surface layer of the drift layer, the position corresponding to the threading dislocation. The electric-field reduction region is an epitaxial layer.

Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Provided is a semiconductor device includes a first semiconductor layer provided on a first main surface of the semiconductor substrate, a plurality of first semiconductor regions selectively provided at upper layer parts of the semiconductor layer, a second semiconductor region selectively provided at an upper layer part of each of the first semiconductor regions, a second semiconductor layer provided on a JFET region corresponding to the first semiconductor layer between the first semiconductor regions, and configured to cover at least a part of the JFET region, a gate insulating film covering the first semiconductor regions and the second semiconductor layer, a third semiconductor layer provided on the second semiconductor layer, a gate electrode provided on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film, a contact hole penetrating through the gate insulating film and the interlayer insulating film, at least the second semiconductor region being exposed to a bottom part thereof, a first main electrode provided on the interlayer insulating film, and configured to electrically connect to the second semiconductor region via the contact hole, and a second main electrode provided on a second main surface of the semiconductor substrate.

Semiconductor device and method of manufacturing same

A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.

Semiconductor device with silicon layer containing carbon

Method of manufacturing a MISFET on an SOI substrate

Growing community of inventors

Tokyo, Japan

Toshiaki Iwamatsu