United Microelectronics Corp.

Other

Tony Lin

Jih-Wen Chou

Wen-Kuan Yeh

Water Lur

Coming Chen

Heng-Sheng Huang

Shih-Wei Sun

Hua-Chou Tseng

Tri-Rung Yew

Yimin Huang

Tung-Po Chen

Jenn Tsao

C C Hsue

Ming-Yin Hao

Juan-Yuan Wu

Kuo-Tai Huang

Horng-Nan Chern

Chih-Yung Lin

Chien-Chao Huang

Jung-Tsung Tseng

Jiun-Yuan Wu

Chin-Lai Chen

Abula Yu

Jung-Chun Lin

Alice Chao

Hsiao-Lin Lu

Yoyi Gong

A foldable dust collector of the present invention includes a supporting portion, a case and an air pump. The supporting portion is foldable. The case is disposed on the supporting portion. The case is pivotable with respect to the supporting portion. The air pump is disposed on the case. The air pump is used for drawing air into the case. Therefore, the foldable dust collector of the present invention can be transformed. A width of the foldable dust collector is changeable. As such, the foldable dust collector is easier to be stored or be transported. Moreover, the foldable dust collector can be used in a small space.

Foldable dust collector

The present invention provides an air filter including a main body, a pressure fan, a filter mode and a fixing assembly. The main body has a containing room, an entrance hole and an exit hole. The pressure fan is disposed in the containing room. The filter mode includes a first filter layer, a second filter layer and a frame body. The first filter layer is disposed in the entrance hole, and the second filter layer is disposed in the frame body. As such, users can select to use only the first filter layer or both filter layers at one time. Moreover, users only need to let the frame body pivot to a position away from the entrance hole so that users can change the filter layers faster and easier.

Air filter

A dust collector of the present invention includes a main body, a first dust container, and two lifting apparatuses. The main body includes a shell, an expandable pipe, and a lid. The expandable pipe, which is vertically expandable, is connected between the shell and the lid. The first dust container is detachably disposed on the main body and is used to be selectively covered by the lid. The two lifting apparatuses respectively include a base, a linking up mechanism, and an operating rod. The two bases are respectively fixed on two sides of an outer wall surface of the shell. The operating rod is movably disposed on the base. One end of the linking up mechanism is disposed on the operating rod, and the other end is fixed on the lid. Thereby, the lifting apparatus can horizontally lift the lid.

Dust collector

A dust collector includes a shell, an exit tube, an inner tube, a suction device, a first dust container, a bypass tube and a first dust bag. The shell defines a first receiving room therein. The exit tube defines an exit passage therein. The inner tube defines a connection passage which has a first opening and a second opening. The first opening communicates the first receiving room, and the second opening communicates the exit passage. The suction device provides the exit passage with a negative pressure. The first dust container defines a second receiving room therein. A mesh is disposed on a bottom surface of the first dust container to divide the second receiving room into a first chamber and a second chamber. The bypass tube defines a bypass passage therein, and it communicates the connection passage with the second chamber. The first dust bag is disposed in the first chamber.

A method for fabricating a transistor having a fully silicided gate is described. A silicon substrate with a semi-finished transistor formed thereon is provided, wherein the transistor comprises a gate dielectric film, a silicon gate, a cap layer on the silicon gate, a spacer and a source/drain region. A raised source/drain is formed on the source/drain region, and then the cap layer is removed. Subsequently, a full silicidation process is performed to fully silicide the silicon gate.

Method for fabricating transistor having fully silicided gate

A detachable laser pointer is constructed to include a mounting base, the mounting base having a smoothly arched rear coupling groove for coupling to the shaft of a golf putter and a locating plate of C-shaped cross section upwardly extended from the smoothly arched coupling groove for plugging in between the shaft and grip of the golf putter and a front receiving groove, a joint rotatably coupled to the receiving groove, a laser module pivoted to the joint and adapted for emitting a laser beam to aim the putter head of the golf putter to the hole.

Detachable laser pointer for golf putter

A method of manufacturing a low-leakage, high-performance device. A substrate having a gate electrode thereon is provided. A lightly doped, high-energy implantation is conducted to form a lightly doped source/drain terminal in the substrate. An offset spacer is formed on each sidewall of the gate electrode. A heavily doped implantation is conducted to form a heavily doped source/drain terminal in the substrate. The heavily doped source/drain terminal has a depth smaller than the lightly doped source/drain terminal. A protective spacer structure is formed on each sidewall of the gate electrode. A deep-penetration source/drain implantation is carried out to form a deep source/drain terminal in the substrate.

Method of manufacturing low-leakage, high-performance device

A MOS transistor includes a substrate, an insulation layer, a gate and a dielectric layer. The substrate includes a drain and a source separately positioned on the surface of the substrate. The insulation layer is positioned on the surface of the substrate between the drain and the source. The gate includes a conducting layer positioned on the insulation layer having a bottom side, a top side, a left side and a right side, and a metallic silicide layer positioned on the top side of the conducting layer wherein the width of the metallic silicide layer is greater than that of the bottom side of the conducting layer. The dielectric layer covers the drain, the source and the metallic silicide layer. The transistor includes at least one empty side slot positioned between the dielectric layer and the left side or right side of the conducting layer below the metallic silicide layer.

MOS transistor with two empty side slots on its gate and its method of formation

A method for forming doped p-type gate is disclosed as the following description. The method includes that, firstly, a semiconductor substrate is provided. The semiconductor substrate is etched to form a concave portion as a shallow trench isolation. A first silicon dioxide is filled into the shallow trench isolation. A n-type well is formed into the semiconductor substrate. A silicon germanium layer, named as the doped p-type layer is formed on the surface of semiconductor substrate and the surface of shallow trench isolation. A silicon nitride layer, named as the anti-reflection layer is formed on the surface of silicon germanium layer. The portions of silicon nitride layer and the portions of silicon germanium layer are etched as a gate region. The source/drain extension is formed. A second silicon dioxide layer is deposited over the surface of semiconductor substrate and the surface of nitride layer. The second silicon dioxide layer is etched as a spacer beside the sidewall of gate region. A source/drain region is formed into the semiconductor substrate. The silicon nitride layer is removed. Finally, salicide region is formed into the source/drain region and upon the surface of silcion layer to complete the silicon gate structure.

Method for forming doped p-type gate with anti-reflection layer

A SEG combined with tilt implant method for forming semiconductor device is disclosed. The method includes providing a semiconductor structure which comprises an active area in between isolation regions in a substrate with the active area having a gate electrode formed thereon, wherein a spacer is formed on the sidewall of said gate electrode. Then, selective epitaxial growth regions are formed on the active area and the gate electrode. Next, the active area is implanted with an angle to form source/drain regions beside the bottom edge of the gate electrode. Then, the salicide process and backend processes are performed.

SEG combined with tilt side implant process

A method for fabrication a shallow trench isolation (STI) structure by combining uses of a STI process and a local oxidation (LOCAS) process is provided. The method includes forming a first liner oxide layer over a substrate, on which a patterned hard material layer is formed. A hard spacer is formed on each sidewall of the hard material layer. A LOCOS structure is formed on the substrate other than the hard spacer and the hard material layer. Then, the hard spacer is removed to expose a portion of the pad oxide on the substrate. A trench is formed in the substrate on each side of the LOCOS structure. A conformal second liner oxide layer is formed on the inner surface of the trench. The trench is filled with a polysilicon layer, having a surface higher than the substrate surface. A second thermal process is performed to oxidize the polysilicon layer so as to merge the LOCOS structure to cover the surface of the polysilicon layer. The hard material layer is removed to form the isolation structure of the invention.

Method for fabricating an isolation structure including a shallow trench isolation structure and a local-oxidation isolation structure

A method for forming semiconductor devices is disclosed. The method of the present invention includes providing a semiconductor substrate, followed by forming shallow trench isolation (STI) process, and then a dummy gate is formed by silicon nitride layer which is deposited and defined. With appropriate wet etching, this dummy poly can be removed. After local punch-through implantation, reverse offset spacer is formed to reduce Cgd (capacitance is between gate and drain) and poly-CD (critical dimension). Polysilicon is deposited followed by polysilicon CMP. After thick Ti-salicidation, the usual CMOS (Complementary Metal-Oxide-Semiconductor) processes are proceeded.

Method for forming a semiconductor device by using reverse-offset spacer process

A method of fabricating a MOS transistor having SEG Si. After the formation of a gate and a spacer and before a source/drain region is formed, a selective epitaxial growth (SEG) Si is deposited over the substrate. The spacer is then removed to form an ultra shallow junction in the exposed substrate covered by the spacer after the formation of the SEG Si.

Method of fabricating a MOS transistor having SEG silicon

A fabrication method for a metal oxide semiconductor (MOS) transistor involves forming gate oxide layers of different thicknesses on a core region and a input/output (I/O) region. After forming wells in the substrate, two implantation regions for providing a threshold voltage (V,) adjustment and an anti-punch through layer are formed respectively in a P-well and a N-well of the core region as well as a P-well and a N-well of the I/O region. The method involves forming a pattern mask on the gate oxide layer, wherein the pattern mask has an opening, which may be a channel that corresponds to the P-well of the core region. With the pattern mask serving as an ion implantation mask, two implantation regions for providing the V,adjustment and the anti-punch through layer are formed in the P-well of the core region. After the pattern mask is removed, the steps described above are repeated in order to form implantation regions in other regions, but the sequence of the steps can be swapped around at will. The subsequent process for the MOS transistor is then performed.

Method of fabricating a MOS transistor with local channel ion implantation regions

The present invention provides a method of forming a PMOS transistor or an NMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate and a gate positioned on a predetermined area of the silicon substrate. First, a protection layer of uniform thickness made of silicon nitride is formed on the semiconductor wafer to cover the surface of the gate. Then, a first ion implantation process is performed to form a first ion implantation layer with a first predetermined thickness on the silicon substrate around the gate. Then, an RCA cleaning process is performed to remove impurities on the semiconductor wafer. Next, a spacer is formed around the gate. Finally, a second ion implantation process is performed to form a second ion implantation layer with a second predetermined thickness on the silicon substrate around the gate. The second ion implantation layer is used as a source or drain (S/D) of the MOS transistor. The portion of the first ion implantation layer that is not covered by the second ion implantation layer is used as a lightly doped drain (LDD). The protection layer is used to protect the surface of the silicon substrate from being etched during the RCA cleaning process so as to prevent an increase of the electrical resistance of the LDD.

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Kaohsiung Hsien, Taiwan

Tony Lin