Kla-tencor Technologies Corporation

Kla Tencor Corporation

Tony DiBiase

Mei H Sun

Mark Wiltse

Wayne Glenn Renken

Zachary Reid

A method for constructing an error map for a lithography process, by constructing a first error map using spatial error data compiled on a lithography tool used in the lithography process, and constructing a second error map using spatial error data compiled on a mask used in the lithograph process, and then combining the first error map and the second error map to produce an overall error map for the lithography process. In this manner, the spatial error is determined prior to committing product to the process, and excessive error can be corrected or otherwise resolved prior to such commitment. In various embodiments, the spatial error data includes lens error data and stage movement error data. In some embodiments the spatial error data compiled on the mask is constructed by comparing mask pattern placement data to mask pattern source files. Some embodiments include the step of adjusting process variables to reduce errors represented in the overall error map.

Assessing critical dimension and overlay tolerance

An instrument for measuring a parameter comprises a substrate, a plurality of sensors carried by and distributed across a surface of the substrate that individually measure the parameter at different positions, an electronic processing component carried by the substrate surface, electrical conductors extending across the surface connected to the sensors and the electronic processing component, and a cover disposed over the sensors, electronic processing component and conductors. The cover and substrate have similar material properties to a production substrate processed by a substrate processing cell. The instrument has approximately the same thickness and/or flatness as the production substrate. The instrument may be subjected a substrate process and one or more parameters may be measured with the instrument during the process. The behavior of a production wafer in the substrate process may be characterized based on measurements of the parameters made with the one or more sensors.

Process condition measuring device

A method of inspecting a pattern on a substrate, by extracting boundary locations from design data for repeating blocks within the pattern, inspecting the substrate at only the boundary locations of the repeating blocks, detecting alignment errors at the boundary locations, comparing the alignment errors to a threshold, and flagging the alignment errors that exceed the threshold. In this manner, the alignment errors that were of no consequence in larger design rule devices can be detected, and a determination can be made as to whether they adversely impact the proper operation of the integrated circuit that will eventually be formed from the pattern. By performing the inspection only on the boundary locations, a much higher magnification can be used than what would be reasonably possible for an inspection of the entire substrate.

Intelligent stitching boundary defect inspection

A method for reducing overlay error in a photolithographic process, by providing a substrate having a permanent layer with a first pattern disposed therein, coating the substrate with photoresist, exposing the photoresist to a second pattern, while measuring temperatures at a plurality of different first positions across the substrate, developing the second pattern in the photoresist, measuring overlay errors between the first and second patterns at a plurality of different second positions across the substrate, correlating the overlay errors with temperatures by position on the substrate, determining any relationship indicated between the correlated overlay errors and temperatures, and adjusting at least one temperature controlling aspect of the photolithographic process in response to any relationship determined.

Temperature effects on overlay accuracy

Cleaning and reclaiming nano-imprint templates using environment friendly methods and systems is disclosed. A template may be cleaned by a combination of exposure to activated gaseous species followed by rinsing with oxygenated or hydrogenated DI water and exposure to reactive plasma to remove organic contaminant. Contaminant may be removed by forming a coating film of a water soluble polymer on the template and then peeling off the coating film. Organic residue from the film may be removed using oxygenated plasma.

Environment friendly methods and systems for template cleaning and reclaiming in imprint lithography technology

A combined overlay target and methods for its use are disclosed. The combined overlay target includes a grating-type overlay target and an image placement error target having substantially perpendicular features with spaced apart edges. The grating-type target and the image placement error target have a common centroid and are sufficiently separated that the grating-type overlay target does not interfere with measurement of image placement error.

Registration target design for managing both reticle grid error and wafer overlay

A process which addresses the problem of transient defects comprises first processing one or more test chips on a substrate to reveal one or more potential transient defects during subsequent processing of all of the chips on the substrate; identifying the exact locations of such potential transient defects on one or more chips of a silicon substrate; forming a file containing the coordinates of each potential transient defect on the chip; converting the file into a CAD image layer capable of displaying such potential transient defects; and displaying such potential transient defects superimposed over a CAD image of the actual circuit to permit visual inspection of the compound CAD image and to permit optional action to be taken in view of such potential transient defects. In another embodiment of the invention, the file containing the locations of the potential transient defects is transmitted to a metrology apparatus such as a critical dimension (CD) scanning electron microscope (SEM) which monitors the potential transient defect addresses during processing of the chip. The two embodiments of the invention may be practiced in the alternative or in combination with one another.

Process for locating, displaying, analyzing, and optionally monitoring potential transient defect sites in one or more integrated circuit chips of a semiconductor substrate

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San Jose, CA, United States of America

Tony DiBiase