Actel Corporation, Inc.

Applied Materials, Inc.

Tong Liu

Jung-Cheun Lien

Sheng Feng

Eddy C Huang

Chung-Yuan Sun

Naihui Liao

Weidong Xiong

Ajay Kumar

Saravjeet Singh

Madhava Rao Yalamanchili

Puneet Bajaj

Khalid Mohiuddin Sirajuddin

Wei-Sheng Lei

Brad Eaton

Qian Fu

Rohit Mishra

Jivko Dinev

Radhe Agarwal

Sangjun Park

Feng Qiao

Zili Zhang

Sonal A Srivastava

A method and system for etching high aspect ratio structures in a semiconducting processing chamber are disclosed herein. In one example, a method of patterning a substrate comprises etching the substrate to form a recess, depositing a passivation layer on sidewalls of the recess, treating the passivation layer, and etching the recess to a second depth. The substrate etch forms a recess to a first depth, the substrate having a mask layer disposed thereon. The treating of the passivation layer is for removal of a clogging material formed from an etch byproduct on the mask layer. The etching the recess to a second depth while maintaining a minimum variation of a recess sidewall width.

Method for etching high aspect ratio structures

Embodiments described herein generally relate to a substrate processing system and related methods, such as an etching/deposition method. The method comprises (A) depositing a protective layer on a first layer disposed on a substrate in an etch reactor, wherein a plasma source power of 4,500 Watts or greater is applied while depositing the protective layer, (B) etching the protective layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the protective layer, and (C) etching the first layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the first layer, wherein a time for the depositing a protective layer (A) comprises less than 30% of a total cycle time for the depositing a protective layer (A), the etching the protective layer (B), and the etching the first layer (C).

Increased deposition efficiency and higher chamber conductance with source power increase in an inductively coupled plasma (ICP) chamber

In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation. The laser scribe process may be used to cleanly remove a mask layer, organic and inorganic dielectric layers, and device layers. The laser etch process may then be terminated upon exposure of, or partial etch of, the wafer or substrate. In embodiments, a multi-plasma etching approach is employed to dice the wafers where an isotropic etch is employed to improve the die sidewall following an anisotropic etch. The isotropic etch removes anisotropic etch byproducts, roughness, and/or scalloping from the anisotropically etched die sidewalls after die singulation.

Laser scribing and plasma etch for high die break strength and clean sidewall

The present disclosure provides methods for etching through-silicon vias (TSVs) in a substrate. The method employs a cyclic polymer passivation layer deposition, depassivation process and plasma etching process. By alternating the duration performed in the plasma etching process and the polymer passivation deposition process during the TSVs formation process, a good sidewall profile and via depth control may be obtained.

Methods for etching through-silicon vias with tunable profile angles

A method for testing FPGA routing circuitry having a plurality of first sets of tracks having programmably connectable individual track segments includes providing a global control signal to simultaneously turn on all of the programmable elements in at least two of the first sets of tracks, defining individual test inputs to apply to the first end of each of the at least two of the first sets of tracks, determining an expected logic result for a selected logical combination of the individual test inputs, applying the individual test inputs to the first end of each of the at least two of the first sets of tracks, performing the selected logical combination on the second ends of the at least two of the first sets of tracks to generate an actual logic result, and flagging an error if the actual result is not identical with the expected logic result.

Tileable field-programmable gate array architecture

An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

A freeway routing system that connects interface groups in said field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals to the input ports of at least one interface group in a first tile of the field programmable gate array and configured to transfer signals from the output ports of other tiles in the field programmable gate array. The first set of conductors include vertical conductors that form intersections horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of horizontal conductors to one of the vertical conductors.

Freeway routing system for a gate array

An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each file comprises a plurality of functional and interface groups and a primary routing structure, which is coupled to the functional and interface groups and is configured to receive and route primary output signals within at least one FPGA tile, and provide primary input signals to the functional and interface groups. Each functional group is configured to receive input signals, perform logic operations, and generate output signals and is configured to transfer signals from the routing structure to outside of at least one FPGA file, and includes a plurality of input multiplexers configured to select signals received from outside at least one FPGA tile and provide signals to the routing structure inside at least one FPGA tile.

Inter-tile buffer system for a field programmable gate array

An inter-tile buffering system for a field programmable gate array (FPGA) comprising a plurality of FPGA tiles arranged in rows and columns. Each tile comprises a plurality of functional and interface groups and a primary routing structure, which is coupled to the functional and interface groups and is configured to receive and route primary output signals within at least one FPGA tile, and provide primary input signals to the functional and interface groups. Each functional group is configured to receive input signals, perform logic operations, and generate output signals and is configured to transfer signals from the routing structure to outside of at least one FPGA tile, and includes a plurality of input multiplexers configured to select signals received from outside at least one FPGA tile and provide signals to the routing structure inside at least one FPGA tile.

An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.

An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The routability of the regular routing structure is maximized by depositing switches according to designators. This novel designation method provides the same routability with approximately half the switches. Thus, further reduction in routing area is achieved. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.

The invention relates to an inter-tile buffering system for a field programmable gate array. The field programmable gate array is comprised of the following. A plurality of field programmable gate array tiles are arranged in an array of rows and columns. Each of said field programmable gate array tiles comprises a plurality of functional groups and a plurality of interface groups, and a primary routing structure. The primary routing structure is coupled to said functional groups and interface groups and is configured to receive primary output signals, route primary output signals within said at least one field programmable gate array tile, and provide primary input signals to said functional groups and interface groups. Each functional group is configured to receive primary input signals, perform a logic operation, and generate primary output signals. Each interface group is configured to transfer signals from said primary routing structure to outside of said at least one field programmable gate array tile, and includes a plurality of input multiplexers configured to select signals received from outside of said at least one field programmable gate array tile and provide signals to the primary routing structure inside said at least one field programmable gate array tile. Said primary routing structure comprises a horizontal bus and a vertical bus. A horizontal buffer is located between each column of field programmable gate array tiles and is coupled to the primary routing structure. A vertical buffer is located between each row of field programmable gate array tiles and is coupled to the primary routing structure.

The disclosed system relates to a freeway routing system and a fast-freeway routing system for a field programmable gate array. The field programmable gate array comprises a two by two array of field programmable gate array tiles. Each tile comprises: a plurality of functional groups arranged in rows and columns; a plurality of interface groups surrounding the plurality of functional groups such that one interface group is positioned at each end of each row and column, each of the interface groups comprising a set of freeway input and output ports; a freeway set of routing conductors configured to transfer signals to the freeway input ports and from the output ports of the interface groups in each of the field programmable gate array tiles. The freeway set of routing conductors comprises: a plurality of vertical conductors that form intersections with a plurality of horizontal conductors; and programmable bi-directional three state interconnect elements located at the intersections. The fast-freeway routing system comprises: a first group of fast-freeway routing conductors, a second group of fast-freeway routing conductors, a third group of fast-freeway routing conductors, and a fourth group of fast-freeway routing conductors.

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San Jose, CA, United States of America

Tong Liu