Shanghai Huali Microelectronics Corporation

Tong Lei

Yongyue Chen

HaiFeng Zhou

Jingxun Fang

Junhua Yan

Hailan Yi

One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.

Fabrication technology for metal gate

A novel plasma process is introduced as an improvement over conventional plasma processes during formation of spacers for FinFET devices. Under this novel plasma process, an oxide layer is grown over sidewall materials and low energy plasma gas is used for the over-etching of the corner areas of the sidewalls. The oxide layer can effectively protect the sidewall materials during the over-etching by the low energy plasma gas and thus to reduce the aforementioned CD losses introduced by the low energy plasma gas. This improved low energy plasma etching technique can protect the fin structure from CD losses as compared to the conventional low energy plasma process, and also avoid damaging fin silicon structure with reduced Si losses as compared to the conventional high energy plasma process.

Integration process of finFET spacer formation

A method of planarizing a polysilicon gate are provided, comprising: growing a polysilicon gate layer on a substrate with trenches; depositing an oxide layer on the polysilicon gate layer; oxidizing the top portion of the polysilicon gate layer from the flat surface of the oxide layer, so as to form a silicon oxide interlayer in the top portion of the polysilicon gate layer; the bottom of the silicon oxide interlayer is aligned with or lower than the low-lying areas of surface of the polysilicon gate layer; removing the oxide layer and the silicon oxide interlayer, so as to obtain a flat surface of the polysilicon gate layer and avoid a series of problems resulted from the uneven surface in the subsequent processes.

Method of planarizing polysilicon gate

The present invention provides a method for forming a cobalt barrier layer and a metal interconnection process. The method is performed on a surface of a semiconductor device substrate on which metal interconnection lines and an inter-line dielectric layer are formed, and comprises: depositing a dielectric material film on a surface of the inter-line dielectric layer by atomic layer deposition, to densify the surface of the inter-line dielectric layer; removing the deposited dielectric material film, to expose the metal interconnection lines and the densified surface of the inter-line dielectric layer, selectively depositing cobalt on surfaces of the metal interconnection lines to form a cobalt barrier layer. In the present invention, deposition selectivity of cobalt on surfaces of the metal interconnection lines and the inter-line dielectric layer is improved, thus reducing leakage current between metal interconnection lines and improving yield and reliability of the product.

Growing community of inventors

Shanghai, China

Tong Lei