Sandisk Technologies Inc.

Tomoyuki Obu

Tatsuya Hinoue

Tomohiro Uno

Raghuveer S Makala

Rahul Sharangpani

Fei Zhou

Adarsh Rajashekhar

Yusuke Mukae

James K Kai

Jayavel Pachamuthu

Akio Nishida

Shinsuke Yada

Murshed Chowdhury

Seiji Shimabukuro

Takeki Ninomiya

Hiro Kinoshita

Kazutaka Yoshizawa

Atsushi Suyama

Yusuke Yoshida

Marika Gunji-Yoneoka

Yu Ueda

Eisuke Takii

Toshihiro Iizuka

Yasuyuki Aoki

Daewung Kang

Tsuyoshi Hada

Ryusuke Mikami

Luckshitha Suriyasena Liyanage

Daisuke Miyake

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.

Three-dimensional memory device containing compositionally graded word line diffusion barrier layer for and methods of forming the same

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack. A layer stack including a charge storage layer, a tunneling dielectric layer, a semiconductor material layer, and a dielectric material layer is formed in the memory openings. The dielectric material layer may include a doped silicate glass layer. A doped silicate glass pillar can be formed at a bottom portion of each memory opening, and a bottom portion of the semiconductor material layer can be converted into a source region by outdiffusion of dopants from the doped silicate glass pillar. Alternatively, the semiconductor material layer can be heavily doped, and can be recessed to form a source region.

Three-dimensional memory devices containing structures for controlling gate-induced drain leakage current and method of making the same

A first field effect transistor and a second field effect transistor are formed on a substrate. A silicon nitride liner is formed over the first field effect transistor and the second field effect transistor. An upper portion of the silicon nitride liner is converted into a thermal silicon oxide liner. A lower portion of the silicon nitride liner remains as a silicon nitride material portion. A first portion of the thermal silicon oxide liner is removed from above the second field effect transistor, and a second portion of the thermal silicon oxide liner remains above the first field effect transistor. Selective presence of the silicon oxide liner provides differential stress within the channels of the first and second field effect transistors, which can be employed to optimize performance of different types of field effect transistors.

Field effect transistors having different stress control liners and method of making the same

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming memory stack structures through the alternating stack, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel, forming backside recesses by removing the sacrificial material layers selective to the insulating layers and the memory stack structures, forming a backside blocking dielectric layer in the backside recesses, forming an amorphous titanium oxide layer on surfaces of the backside blocking dielectric layer in the backside recesses, and forming tungsten word lines in the backside recesses using a fluorine-free tungsten-containing precursor gas.

Three-dimensional memory device containing fluorine-free tungsten&#x2014;word lines and methods of manufacturing the same

An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the alternating stack. An optional silicon-containing epitaxial pedestal and a memory film are formed in each memory opening. After forming an opening through a bottom portion of the memory film within each memory opening, a germanium-containing semiconductor layer and a dielectric layer is formed in each memory opening. Employing the memory film and the dielectric layer as a crucible, a liquid phase epitaxy anneal is performed to convert the germanium-containing semiconductor layer into a germanium-containing epitaxial channel layer. A dielectric core and a drain region can be formed over the dielectric layer. The germanium-containing epitaxial channel layer is single crystalline, and can provide a higher charge carrier mobility than a polysilicon channel.

Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof

A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line by selectively forming a conductive oxide material layer adjacent the word line, and forming a semiconductor material layer adjacent the bit line, and forming a memory cell comprising the nonvolatile memory material at an intersection of the bit line and the word line.

Methods and apparatus for three-dimensional nonvolatile memory

Electrically conductive layers for control gate electrodes of a vertical memory device can be vertically spaced by cavities to reduce capacitive coupling between neighboring electrically conductive gate electrodes. An alternating stack of first material layers and second material layers can be provided. After replacing the second material layers with electrically conductive layers, the first material layers can be removed to form cavities between the electrically conductive layers. A dielectric material can be deposited with high anisotropic deposition rate to form an insulating spacer. For example, a plasma assisted atomic layer deposition process can be employed to deposit a dielectric spacer that include laterally protruding portions that encapsulate the cavities at each level between neighboring pairs of electrically conductive layers. A contact via structure can be formed in the insulating spacer to provide electrical contact to a source region.

Three-dimensional memory structure employing air gap isolation

Growing community of inventors

Yokkaichi, Japan

Tomoyuki Obu