Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Renesas Technology Corp.

Other

Mitsubushi Denki Kabushiki Kaisha

Tomohide Terashima

Fumitoshi Yamamoto

Gourab Majumdar

Masanori Fukunaga

Kazumasa Satsuma

Masao Yoshizawa

Hiroshi Yamaguchi

Kazuhiro Shimizu

Takeshi Kida

Yasunori Yamashita

Junichi Yamashita

Tetsuya Nitta

Tatsuhiko Nagatani

Tetsuo Takahashi

Sho Tanaka

Yasuhiro Kagawa

Kiyoto Watabe

Kensuke Taguchi

Yasuhiro Yoshiura

Shiori Uota

Eiko Otsuki

Keiichi Furuya

There are provided a transistor including a first semiconductor layer of a first conductivity type, a second semiconductor layer thereabove, a first impurity region of a second conductivity type provided in an upper layer part of the second semiconductor layer, a second impurity region of a first conductivity type provided in an upper layer part of the first impurity region, a gate electrode facing the first impurity region and the second semiconductor layer with a gate insulating film interposed in between, and first and second main electrodes; a parasitic transistor with the second impurity region as a collector, the first and the second semiconductor layers as an emitter, and the first impurity region as a base; a parasitic diode with the first impurity region as an anode, and the first and the second semiconductor layers as a cathode; and a pn junction diode with the first impurity region as an anode, and the second impurity region as a cathode.

Semiconductor device

A semiconductor device includes a main IGBT, a sense, a resistor, a MOSFET and a diode, as main components. The sense IGBT and the main IGBT are connected in parallel with each other. The drain of MOSFET is connected to the gate of the sense IGBT, the source thereof is connected to the gate of the main IGBT, and the gate thereof is connected to the emitter of the sense IGBT and the cathode of diode. One end of the resistor is connected to the gate of the main IGBT and the source of the MOSFET, and the other end of the resistor is connected to the emitter of the main IGBT and the anode of the diode.

There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.

Semiconductor device and method of manufacturing same

A semiconductor device manufacturing method according to the present invention includes a step of arranging a plurality of processing objects on a first tray and a second tray adjacent to the first tray, a plurality of application steps in which application of an application substance to the plurality of processing objects is repeated a certain number of times by emitting the application substance from an application device formed right above a contact position at which the first tray and the second tray contact each other, by swinging the application device along a first direction across the contact position, and by moving the first tray and the second tray in a second direction perpendicular to the first direction, and an interchange step of interchanging the first tray and the second tray in position without changing the directions of the first tray and the second tray corresponding to the second direction, the interchange step being executed at least one time among the plurality of application steps.

Semiconductor device manufacturing method and semiconductor manufacturing apparatus

A semiconductor device includes a substrate, a buried insulating film formed on the substrate, an SOI layer formed on the buried insulating film, an insulating film formed to extend from a top surface of the SOI layer to the buried insulating film and to divide the SOI layer into a first SOI layer and a second SOI layer isolated from the first SOI layer, an element formed in the first SOI layer, and an electrode having at one end thereof a pad located directly above the second SOI layer, the other end of the electrode being connected to the first SOI layer. A cavity region is formed between the buried insulating film and the substrate directly below the first SOI layer. The portion of the buried insulating film directly below the second SOI layer is at least partially in direct contact with the substrate.

On a main surface of a semiconductor substrate, an Nsemiconductor layer is formed with a dielectric portion including relatively thin and thick portions interposed therebetween. In a predetermined region of the Nsemiconductor layer, an N-type impurity region and a P-type impurity region are formed. A gate electrode is formed on a surface of a portion of the P-type impurity region located between the N-type impurity region and the Nsemiconductor layer. In a predetermined region of the Nsemiconductor layer located at a distance from the P-type impurity region, another P-type impurity region is formed. As a depletion layer block portion, another N-type impurity region higher in impurity concentration than the Nsemiconductor layer is formed from the surface of the Nsemiconductor layer to the dielectric portion.

A semiconductor device includes a plurality of floating regions, an insulating layer and a capacitance forming portion. The plurality of floating regions are arranged on a surface of a semiconductor substrate in a row, wherein the plurality of floating regions are provided with insulating regions therebetween. The plurality of floating regions include a first floating region and a second floating region. The second floating region is located farther than the first floating region from an island region of a predetermined potential on the semiconductor substrate. The insulating layer is interposed between each of the plurality of floating regions and a semiconductor material layer of the semiconductor substrate. The capacitance forming portion forms an external capacitance in parallel with the capacitance of the insulating region between the first floating region and the island region of the predetermined potential.

Semiconductor device with reduced potential between adjacent floating regions

In a region located between a collector electrode and a semiconductor substrate, there are a portion where a hollow region is located and a portion where no hollow region is located. Between the collector electrode and the portion where no hollow region is located in the semiconductor substrate, a floating silicon layer electrically isolated by insulating films is formed.

Semiconductor device element formed on SOI substrate comprising a hollow region, and having capacitors in an electric field alleviation region

A semiconductor device supplying a charging current to a charging-target element includes: a semiconductor layer of a first conductivity type; a first semiconductor region of a second conductivity type formed on a main surface of the semiconductor layer and having a first node coupled to a first electrode of the charging-target element and a second node coupled to a power supply potential node supplied with a power supply voltage; a second semiconductor region of the first conductivity type formed in a surface of the first semiconductor region at a distance from the semiconductor layer and having a third node coupled to the power supply potential node; and a charge carrier drift restriction portion restricting drift of charge carrier from the third node to the semiconductor layer.

Semiconductor device supplying charging current to element to be charged

The semiconductor device includes a P-type semiconductor region and an MOS transistor. MOS transistor includes a gate electrode, a collector electrode, a drain electrode, an N-type impurity region and a P-type impurity region. N-type impurity region is electrically connected to the drain electrode. P-type impurity region is electrically connected to the collector electrode. P-type impurity region is electrically connected to the drain electrode. The semiconductor device further includes an N-type impurity region and an electrode. N-type impurity region is electrically connected to the gate electrode. The electrode is formed on the P-type semiconductor region with an insulating film therebetween, and is electrically connected to gate electrode. Thereby, an element footprint can be reduced while maintaining characteristics.

Semiconductor device internally having insulated gate bipolar transistor

A voltage mitigating element mitigating a voltage applied across a gate insulating film in an off state of an insulated gate bipolar transistor (IGBT) is arranged to a gate electrode node of a P-channel MOS transistor provided for suppressing flow-in of holes at the time of turn-off of the IGBT. Withstanding voltage characteristics are improved and an occupation area thereof is reduced while maintaining switching characteristics and a low on-resistance of an insulated gate bipolar transistor.

A semiconductor layer provided on a BOX (buried oxide) layer includes a first P-type region, an N-type region, and an N-type region which together form a diode. A plurality of second P-type regions are provided on a bottom part of the semiconductor layer. A plurality of insulating oxide films are interposed between the plurality of second P-type regions. When the diode is in a reverse-biased state, the second P-type region directly below the N-type region is approximately the same in potential as the N-type region. The second P-type region will be lower in potential relative to this second P-type region directly below the N-type region, as the second P-type region gets nearer to the first P-type region. Electric field concentration can thus be relaxed at an interface between the semiconductor layer and the BOX layer, whereby improvement in breakdown voltage of the diode is realized.

Growing community of inventors

Tokyo, Japan

Tomohide Terashima