Kabushiki Kaisha Toshiba

Micron Technology Incorporated

Sandisk Corporation

Toshiba Memory Corporation

Intel Corporation

Sandisk Technologies Inc.

Other

Kioxia Corporation

Kabushiki Kaisha Sega

Kabushiki Kaishi Toshiba

Tomoharu Tanaka

Noboru Shibata

Ken Takeuchi

Toru Tanzawa

Takashi Mori

Riichiro Shirota

Yoshiyuki Tanaka

Jian Feng Chen

Seiichi Aritome

Yoshihisa Iwata

Yasuo Itoh

Koji Sakui

Tetsuo Endoh

Hiroshi Nakamura

Yutaka Okamoto

Fujio Masuoka

Fumitaka Arai

Hideo Kato

Masamichi Asano

Koichi Kawai

Koji Hosono

Kenichi Imamiya

Huai-Yuan Tseng

Eric N Lee

Shigekazu Yamada

Kishore Kumar Muchherla

James Fitzpatrick

Akira Goda

Ryouhei Kirisawa

Yoshiaki Fukuzumi

Yan Li

Jeffrey W Lutze

Yupin K Fong

Tamio Ikehashi

Shinji Saito

Hiroshi Watanabe

Vishal Sarin

Daniel C Guterman

Aaron S Yip

Krishna Kumar Parat

Naoki Yasuda

Graham Richard Wolstenholme

Haitao Liu

Hiroyuki Nagashima

Masaki Momodomi

Hideko Odaira

Gertjan Hemink

Kazunori Ohuchi

Hiroto Nakai

Susumu Fujimura

Kaoru Tokushige

Khandker N Quader

Dung Viet Nguyen

Toshio Yamamura

Susumu Shuto

Midori Morooka

Dave Scott Ebsen

Hiroshi Sukegawa

Yoshihiko Kamata

Hiroaki Hazama

David Scott Ebsen

Takehiro Hasegawa

Prashant S Damle

Tetsuhiko Mizoguchi

Shigeyoshi Watanabe

Shafqat Ahmed

Masaki Fujiu

Kazunori Kanebako

Toshiro Sato

Akira Toriumi

Takeaki Sato

Yuji Ide

Michael M Abraham

Hiroyuki Dohmae

Hideki Sumihara

Yuichi Einaga

Atsushi Inoue

Ching-Huang Lu

Junichi Miyamoto

Jun Fujiki

Shuji Tanaka

Hideko Oodaira

Yoshihisa Sugiura

Giovanni Maria Paolucci

Masatsugu Kojima

Ryozo Nakayama

Toshiyuki Mukaiyama

Seiki Saito

Andrew Bickler

Minami Kumazawa

Jian Chen

A memory device includes an array of strings of memory cells, a local bitline coupled with a plurality of the strings of memory cells, and a sense transistor having a gate terminal coupled with the local bitline. The memory device further includes a series of transistors have a data read path between a source line and the sense transistor and between the sense transistor and a global bitline that is coupled with a page buffer. A micropump is integrated within the series of transistors. Control logic is coupled with the series of transistors and to, during a read operation of a memory cell of the array and in response to the sense transistor turning on, activate the micropump to cause a constant read current to flow between the global bitline and the source line.

Capacitive sensing with a micro pump in a memory device

A microelectronic device comprises a stack structure, pillar structures, a conductive plug structure, a sense transistor, and selector transistors. The stack structure comprises a vertically alternating sequence of conductive material and insulative material, and is divided into blocks separated by dielectric slot structures. The blocks individually include sub-blocks horizontally extending in parallel with one another. The pillar structures vertically extend through one of the blocks of the stack structure. Each pillar structure of a group of the pillar structures is positioned within a different one of the sub-blocks of the one of the blocks than each other pillar structure of the group. The conductive plug structure is coupled to multiple of the pillar structures of the group of the pillar structures. The sense transistor is gated by the conductive plug structure. The selector transistors couple the sense transistor to a read source line structure and a digit line structure.

Microelectronic devices, and related memory devices and electronic systems

A read is initiated with respect to a target cell. A pair of adjacent cells includes a first cell and a second cell each adjacent to the target cell. First cell state information is obtained for the first cell and second cell state information is obtained for the second cell. A state information bin is determined by applying a pre-defined operation to the first cell state information and the second cell state information of the respective pair of adjacent cells. The target cell is assigned to the state information bin. Each state information bin defines a read level offset for reading the target cell.

Corrective reads with improved recovery from data retention loss

Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.

Adaptive pre-read management in multi-pass programming

A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

Memory device programming technique for increased bits per cell

A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.

Conditional valley tracking during corrective reads

Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

Apparatus with non-linear delay variations for scheduling memory refresh operations and methods for operating the same

A memory device includes an array of memory cells associated with wordlines and control logic. The control logic performs operations that cause a corrective read operation to be performed at a selected memory cell. The operations include: causing a first voltage to be applied to a first wordline associated with the selected memory cell; causing a second voltage, having a lower magnitude than the first voltage, to be applied to wordlines adjacent to the first wordline and associated with each of two neighbor memory cells of the selected memory cell; in response to determining that current flows through the two neighbor memory cells and the selected memory cell between a bitline and a source line of the array, identifying a first corrective read voltage; and causing the first corrective read voltage to be applied to the first wordline during a read operation for the selected memory cell.

Fast two-sided corrective read operation in a memory device

Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

Quick charge loss mitigation using two-pass controlled delay

Memories might include an array of memory cells including a string of series-connected split-gate memory cells, and a controller configured to cause the memory to selectively activate a first memory cell portion of a selected split-gate memory cell of the string of series-connected split-gate memory cells in response to a data state of the first memory cell portion of the selected split-gate memory cell and deactivate a second memory cell portion of the selected split-gate memory cell, and activate a second memory cell portion of each remaining split-gate memory cell of the string of series-connected split-gate memory cells while selectively activating the first memory cell portion of the selected split-gate memory cell and deactivating the second memory cell portion of the selected split-gate memory cell.

Memories having split-gate memory cells

A microelectronic device comprises local digit line structures, global digit line structures, source line structures, sense transistors, read transistors, and write transistors. The local digit line structures are coupled to strings of memory cells. The global digit line structures overlie the local digit line structures. The source line structures are interposed between the local digit line structures and the global digit line structures. The sense transistors are interposed between the source line structures and the global digit line structures, and are coupled to the local digit line structures and the source line structures. The read transistors are interposed between and are coupled to the sense transistors and the global digit line structures. The write transistors are interposed between and are coupled to the global digit line structures and the local digit line structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

3D NAND flash memory devices and related electronic systems

A memory device includes a memory array of memory cells and control logic operatively coupled to the memory array. The control logic to perform memory erase operations including: performing a true erase sub-operation by causing multiple pulse steps to be applied sequentially to a group of memory cells of the memory array, wherein each sequential pulse step of the multiple pulse steps occurs during a pulse-step period and at a higher voltage compared to an immediately-preceding pulse-step; in response to detecting an erase suspend command during a pulse step, suspending the true erase sub-operation at a start of a subsequent pulse-step period after the pulse step; and resuming the true erase sub-operation at an end of the subsequent pulse-step period.

Memory true erase with pulse steps to facilitate erase suspend

A device includes a memory array with first memory cell and second memory cell, and control logic, operatively coupled with the memory array, to cause a first threshold voltage (Vt) state read out of the first memory cell to be converted to a first integer value and a second Vt state read out of the second memory cell to be converted to a second integer value; index, within a decoding table using the first integer value and the second integer value, to determine a set of three logical bits; and output, as a group of logical bits to be returned in response to a read request, the set of three logical bits with a second set of logical bits corresponding to the first Vt state.

Encoding and decoding data bits stored in a combination of multiple memory cells

Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a substrate, a first deck including first memory cell strings located over the substrate, a second deck including second memory cell strings and located over the first deck, first data lines located between the first and second decks and coupled to the first memory cell strings, second data lines located over the second deck and coupled to the second memory cell strings, and first and second circuitries. The first and second data lines extending in a direction from a first portion of the substrate to a second portion of the substrate. The first buffer circuitry is located in the first portion of the substrate under the first memory cell strings of the first deck and coupled to the first data lines. The second buffer circuitry is located in the second portion of the substrate under the first memory cell strings of the first deck and coupled to the second data lines.

Multi-deck memory device including buffer circuitry under array

Growing community of inventors

Yokohama, Japan

Tomoharu Tanaka