Pdf Solutions, Incorporated

Tomasz Brozek

Christopher Hess

Larg H Weiland

Rakesh Vallishayee

Indranil De

Jeremy Cheng

Dennis Ciplickas

Jonathan Haigh

Sherry F Lee

John Kibarian

Kimon Michaels

Hans Eisenmann

Sheng-Che Lin

Stephen Lam

Vyacheslav Rovner

Andrzej Strojwas

Markus Rauscher

Carl Taylor

Conor O'Sullivan

Timothy Fiscus

Marcin Strojwas

Simone Comensoli

Nobuharu Yokoyama

Marci Liao

Hideki Matsuhashi

Kelvin Doong

Matthew Moe

Sharad Saxena

Yuan Yu

Meindert Martin Lunenborg

Michele Quarantelli

Mike Kyu Hyon Pak

Hendrik Schneider

Amit Joag

Alberto Piadena

SiewHoon Ng

A novel system for in-product Bias Temperature Instability (BTI) characterization that allows for characterization of transistor degradation rates is disclosed; it is self-testing and can be embedded in real products without impacting the host functionality. The test data collected during product chip testing (at Electrical Wafer Sort) can be used for identification of abnormal material and for material disposition, or to predict the chip aging rate and premature failure risk due to BTI degradation. The system can also collect the data from the real time device aging in the field, during the host chip operational lifetime. The system is equipped with local programmable power supply generation and self-test capabilities to allow concurrent operations with the host application. The Devices Under Test (DUTs) consist of standard cell-based Ring Oscillators (ROs) which have the unique capability of decoupling the BTI effects on N-type and P-type MOSFET transistors. New switching circuitry is implemented that provides for minimal delay between the stress and measurement phases, thus giving the system the capability of fully characterizing the BTI relaxation dynamic.

Embedded system to characterize BTI degradation effects in MOSFETs

An IC that includes a contiguous standard cell area with a 4x3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

IC with test structures and e-beam pads embedded within a contiguous standard cell area

An IC that includes a contiguous standard cell area with a 4&#xd7;3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

IC with test structures and E-beam pads embedded within a contiguous standard cell area

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas.

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas

Described are test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies.

Test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies

An IC includes a contiguous standard cell area with first, second, and third TS-GATE-short-configured test area geometries disposed therein. In some embodiments, the contiguous standard cell area may further include: fourth and fifth TS-GATE-short-configured test area geometries, and/or other test area geometries, such as tip-to-tip-short, tip-to-side-short, diagonal-short, corner-short, interlayer-overlap-short, via-chamfer-short, merged-via-short, snake-open, stitch-open, via-open, or metal-island-open.

IC with test structures embedded within a contiguous standard cell area

Described here is an apparatus and method of testing a vertical (3D) semiconductor memory structure coupled between word lines and bit lines, by means of a direct connections of a plurality of test pads to word lines and bit lines of the memory structure on memory product wafer. Such connections are created by modified patterns of metal lines through contacts and vias created on the memory product wafer. The described apparatus and method are used for detecting electrical continuity (opens and shorts) in the memory structure, calculating resistance of selected word lines or bit cell strings, or performing more complex tests of memory bit cell transistors. The result of this detection can then be used to find defective regions or memory cells in the semiconductor memory structure. Such a testing device may be referred to as a direct testing system.

Method and apparatus for direct testing and characterization of a three dimensional semiconductor memory structure

An apparatus and method for testing two-terminal memory elements organized as a cross-point memory array. The apparatus allows functional testing of two-terminal memory elements organized as a cross-point memory array, and built in a short flow manufacturing process. The proposed apparatus substantially eliminates the use of any type of additional active or passive switches, selectors, or decoders. A large number of memory elements of various memory types including planar (two dimensional) or three dimensional memory structures can be tested without the need of manufacturing selectors or running the full flow process.

Passive array test structure for cross-point memory characterization

Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements ('NCEM') of fill cells that contain structures configured target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such processes may involve evaluating Designs of Experiments ('DOEs'), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with a moving stage and beam deflection to account for motion of the stage.

Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-tip short, via-chamfer short, and corner short test areas, using a charged particle-beam inspector with beam deflection to account for motion of the stage

An IC includes first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements ('NCEM'). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of corner shorts.

Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells

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Morgan Hill, CA, United States of America

Tomasz Brozek