International Business Machines Corporation

Globalfoundries Inc.

Advanced Micro Devices Corporation

Elpis Technologies Inc.

Tom C Lee

Robert J Gauthier, Jr

Souvick Mitra

Christopher Stephen Putnam

JunJun Li

Michel J Abou-Khalil

Jeffrey P Gambino

Timothy Dooling Sullivan

Zhong-Xiang He

James Paul Di Sarro

Fen Chen

Anthony K Stamper

Baozhen Li

Christopher David Muzzy

Robert Russell Robison

Cathryn Jeanne Christiansen

Chih-Chao Yang

Lawrence Alfred Clevenger

William Joseph Murphy

You Li

Junjun Li

Richard Steven Kontra

Gerald Matusiewicz

Kevin Shawn Petrarca

Ronald G Filippi

Edward Crandal Cooney, Iii

William Thomas Motsiff

Kaushik Chanda

Rahul Mishra

Hazara Singh Rathore

Jonathan Daniel Chapple-Sokol

Paul Stephen McLaughlin

Kimball M Watson

Du Binh Nguyen

Birendra N Agarwala

David C Thomas

Jason Paul Gill

Andrew P Cowley

Jean E Wynne

Andreas Scholze

Karl W Barth

Theodore M Levin

Dinesh A Badami

Theodorus E Standaert

William R Tonti

Chengwen Pei

Kai D Feng

Xiao Hu Liu

Wagdi William Abadeer

Alvin Wayne Strong

Daniel Scott Vanslette

Ronald Jay Bolam

John Chester Malinowski

Ian McCallum-Cook

Daniel A Delibac

Michael J Abou-Khalil

John J Ellis-Monaghan

John Atkinson Fifield

Kirk David Peterson

Conal Eugene Murray

Thomas L McDevitt

Anil Kumar Chinthakindi

Andrew A Turner

Deborah M Massey

Oliver Aubel

Nathaniel R Chadwick

Travis S Merrill

Lilian Kamal, Legal Representative

Dimitris P Ioannou

Kevin G Petrunich

Joseph E Therrien

Mitra Souvick

Stanley W Polchlopek

Robert J Gautheir

Christopher D c/o Ibm United Kingdom Ltd Muzzy

Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an cathode on a substrate and a anode on the substrate. The anode is in electrical contact with the cathode. The method further includes forming a device between the cathode and the anode. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Structures, methods and applications for electrical pulse anneal processes

Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode

Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.

Integrated circuit structure with continuous metal crack stop

Structures for a chip, as well as methods of fabricating such chip structures. The chip including a portion of a substrate, an active circuit region associated with the portion of the substrate, an interconnect structure on the active circuit region, and a crackstop extending through the interconnect structure. A groove extends through the interconnect structure to the substrate at a location exterior of the crackstop. A stress-containing layer is formed on at least a portion of the groove.

Edge compression layers

Approaches for providing a liner at a via-to-wire interface are provided. A method includes: forming a via opening that exposes an upper surface of a copper wire; forming a titanium liner on the upper surface of the wire; forming a tungsten liner on the titanium liner; and forming a via on the second liner in the via opening.

Titanium tungsten liner used with copper interconnects

A system and method sorts integrated circuit devices. Integrated circuit devices are manufactured on a wafer according to an integrated circuit design using manufacturing equipment. The design produces integrated circuit devices that are identically designed and perform differently based on manufacturing process variations. The integrated circuit devices are for use in a range of environmental conditions, when placed in service. Testing is performed on the integrated circuit devices. Environmental maximums are individually predicted for each device. The environmental maximums comprise ones of the environmental conditions that must not be exceeded for each device to perform above a given failure rate. Each integrated circuit device is assigned at least one of a plurality of grades based on the environmental maximums predicted for each device. The integrated circuit devices are provided to different forms of service having different ones of the environmental conditions based on the grades assigned to each device.

Methodology of grading reliability and performance of chips across wafer

An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.

SCR with fin body regions for ESD protection

Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from electrostatic discharge. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, and a power clamp device coupled with the timing circuit at the node. The capacitor includes a plurality of capacitor elements. The protection circuit further includes a plurality of electronic fuses. Each electronic fuse is coupled with a respective one of the capacitor elements. A field effect transistor may be coupled in parallel with the resistor of the timing circuit, and may be used to bypass the resistor to provide a programming current to any electronic fuse coupled with a capacitor element of abnormally low impedance.

Self-healing electrostatic discharge power clamp

Circuits and methods for providing electrostatic discharge protection. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, a transmission gate configured to selectively connect the node of the timing circuit with the power clamp device, and a control circuit coupled with the node. The control circuit is configured to control the transmission gate based upon whether or not the capacitor is defective. The timing circuit may be deactivated if the capacitor in the timing circuit is defective and the associated chip is powered. Alternatively, the timing circuit may be activated if the capacitor in the timing circuit is not defective.

Electrostatic discharge protection circuit with a fail-safe mechanism

Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires.

Semiconductor structure with thin film resistor and terminal bond pad

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Essex Junction, VT, United States of America

Tom C Lee