Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Vlsi Limited

Tohru Yasuda

Hajime Sato

Akihiro Iwase

Akira Sugiura

Isaya Sobue

Seiji Yamamoto

Hirosuke Koumyoji

Mikio Ishikawa

Chiaki Furukawa

Kazufumi Komura

Shigetaka Asano

Keiichi Fujimura

Katsuyuki Yamada

Takayoshi Nakamura

Nobuyoshi Nakaya

Kanta Yamamoto

Katsumi Furukawa

Hirohisa Nishiyama

A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.

Semiconductor device and operation monitoring method for semiconductor device

A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW-SWconnected between input/output pads P-Pand a testing line Lso that pads in an arbitrary combination, among the off-probe pads P-Pthat are not made in contact with the tester probe Pr, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad Pthat is made in contact with the tester probe Pr, and the leak current of the probes is measured with the tester TS.

Semiconductor device and test method for the same

A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW-SWconnected between input/output pads P-Pand a testing line Lso that pads in an arbitrary combination, among the off-probe pads P-Pthat are not made in contact with the tester probe Prare selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad Pthat is made in contact with the tester probe Prand the leak current of the probes is measured with the tester TS.

Disclosed is a data reading process as well as an improved semiconductor memory device. Input data supplied to the memory device is written in one of memory cells via a pair of bit lines when a write enable signal is active. After writing of the input data is completed, an equalizing circuit is activated to equalize the potential levels of bit lines used in data writing. An output circuit of the memory device is controlled such that the input data is forcibly output as output data from the memory device during the equalization immediately after writing of the input data is completed.

Semiconductor memory device and method for reading data

Growing community of inventors

Kasugai, Japan

Tohru Yasuda