Advanced Micro Devices Corporation

Globalfoundries Inc.

Other

Cypress Semiconductor Corporation

Spansion Llc.

Todd P Lukanc

Christopher A Spence

Fei Wang

Marina V Plat

Luigi Capodieci

Ramkumar Subramanian

Scott Allan Bell

Christopher F Lyons

Hung-Eil Kim

Cyrus E Tabery

Carl P Babcock

Chris Haidinyak

Steven C Avanzino

Zicheng Gary Ling

Sarah McGowan

Joerg Reiss

Simon S Chan

Raymond T Lee

Jerry Cheng

Bhanwar Singh

Matthew S Buynoski

Kurt Taylor

Uzodinma Okoroanyanwu

Takeshi Nogami

Sergey D Lopatin

Christy Mei-Chu Woo

Hao Fang

Darrell M Erb

Kashmir S Sahota

Dirk Dewar Brown

Lynne A Okada

Kai Yang

Tamer Coskun

Asim A Selcuk

Ercan Adem

Christie Marrian

Wiley Eugene Hill

Wai Lo

Piyush Verma

Young-chang Joo

Christopher Heinz Clifford

Chern-Jiann Lee

Chris Schmidt

Hung-Eli Kim

Rithy Hang

Farrokh Omid-Zehoor

Ajay Singhal

Kurt O Taylor

Methods and systems for generating masks for spacer formation are disclosed. As a part of a disclosed method, a predefined final wafer pattern is accessed, areas related to features in the predefined final wafer pattern are identified and a template mask is formed based on the identified areas for forming spacers on a wafer. Subsequently, a mask is formed for use in the removal of portions of the spacers to form an on wafer pattern that corresponds to the predefined final wafer pattern.

Method and system for automated generation of masks for spacer formation from a desired final wafer pattern

A method of designing an optical photomask includes providing a target pattern, correcting the target pattern with an OPC model, adjusting the target pattern and/or the OPC model, and correcting a first corrected pattern. The target pattern indicates a target shape of a pre-pattern opening in a photoresist layer on a semiconductor substrate. Correcting the target pattern includes using an optical proximity correction (OPC) model to generate OPC output information that includes edge placement error (EPE) information, a first corrected pattern, and/or a simulated contour of the pre-pattern opening. Adjusting the target pattern and/or the OPC model includes adjusting with OPC based adjustments that are based on the OPC output information. Correcting the first corrected pattern includes using the OPC model in response to the OPC based adjustments to generate a second corrected pattern.

Methods and systems for designing and manufacturing optical lithography masks

A method of manufacturing an optical lithography mask includes providing a patterned layout design comprising a plurality of polygons, correcting the patterned layout design using optical proximity correction (OPC) by adjusting widths and lengths of one or more of the plurality of polygons, to generate a corrected patterned layout design, converting the corrected patterned layout design into a mask writer-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons, and biasing each polygon in the plurality of polygons with a bias that accounts for large-scale density values of the patterned layout design, to generate a biased, mask writer-compatible layout design.

Methods for optical proximity correction in the design and fabrication of integrated circuits

A method of forming an electronic device can include forming a patterned mask layer overlying a underlying layer such that the mask layer has a first feature, a second feature, and a third feature, and the first feature is between the second feature and the third feature. The first feature can be spaced apart from the second feature by a first opening in the mask layer, and can be spaced apart from the third feature by a second opening in the mask layer. The method can further include selectively removing portions of the underlying layer under the first opening, the second opening, the second feature, and the third feature, and also removing the second feature and the third feature while leaving substantially all of the first feature and a significant portion of the underlying layer under the first feature.

Method of forming an electronic device including forming features within a mask and a selective removal process

A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques

A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.

System and method for designing an integrated circuit device

According to one exemplary embodiment, a method for increasing manufacturability of a circuit layer includes determining a threshold value for at least one image property from a repetitive section of the circuit layout. According to this embodiment, the method further includes performing a simulated lithographic process using the circuit layout to determine a number of simulated values of the at least one image property for a non-repetitive section of the circuit layout. The method further includes comparing each of the simulated values with the threshold value to determine printability of the non-repetitive section of the circuit layout prior to lithographically printing the circuit layout on a wafer. The method further includes modifying the non-repetitive section of the circuit layout if the threshold value is greater than at least one of the simulated values. By modifying the non-repetitive section of the circuit layout, manufacturability of the circuit layout can be increased.

Method for increasing manufacturability of a circuit layout

There is provided a method of making plurality of features in a first layer. A photoresist layer is formed over the first layer. Dense regions in the photoresist layer are exposed through a first mask under a first set of illumination conditions. Isolated regions in the photoresist layer are exposed through a second mask different from the first mask under a second set of illumination conditions different from the first set of illumination conditions. The exposed photoresist layer is patterned and then the first layer is patterned using the patterned photoresist layer as a mask.

Two mask photoresist exposure pattern for dense and isolated regions

A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.

Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin

A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.

Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results

A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules can be created to disallow layouts demonstrating poor manufacturability.

System and method for design rule creation and selection

Methods of fabricating an integrated circuit on a wafer using dual mask exposure lithography is disclosed. Improved mask image alignment between a first mask image and a second mask image of a dual mask exposure technique can be achieved by aligning the second mask image to a latent image created by an exposure using the first mask image.

Method of lithographic image alignment for use with a dual mask exposure technique

A method of checking a computer generated circuit layout involves selecting vias with at least an edge coincident to an edge of a metal line. Once vias are selected, based upon whether a via touches an edge of a metal line, information regarding the distance between metal lines is determined. Metal lines are resized in the vicinity of a via with an edge touching an edge of a metal line in order to effect a complete connection between the metal line and the via in a manufactured integrated circuit taking into account the information regarding the distance between metal lines. Resized metal lines do not impact metal lines adjacent to the edge that a via was touching because adjacent metal lines are resized to account for a too small separation distance if necessary.

Method and apparatus for generating trenches for vias

The invention includes an apparatus and a method of manufacturing such apparatus including the steps of: forming a layer to be patterned, forming a photosensitive layer over the layer to be patterned, patterning the photosensitive layer to form a pattern including a horizontal line and a vertical line without a space therebetween, transferring the pattern to the layer to be patterned, forming a second photosensitive layer over the pattern, patterning the second photosensitive layer to form a second pattern including a space aligned between the horizontal line and the vertical line, and transferring the second pattern to the layer to be patterned to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a width dimension achievable at a resolution limit of lithography.

Predefined critical spaces in IC patterning to reduce line end pull back

Growing community of inventors

San Jose, CA, United States of America

Todd P Lukanc