Infineon Technologies Ag

Tino Karczewski

Juergen Hoegerl

Christian Schweikert

Adrian Lis

Tao Hong

Ajay Poonjal Pai

Matthias Lassmann

A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.

Lead adapters for semiconductor package

A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the chip, and power terminals arranged along a first side of the package. A second power terminal is arranged between first and third power terminals. The first and third power terminals are configured to apply a first supply voltage. The second power terminal is configured to apply a second supply voltage.

Semiconductor package having symmetrically arranged power terminals and method for producing the same

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Sinzing, Germany

Tino Karczewski