Mosel Vitelic Corporation

Promos Technologies, Inc

Mosel Inc.

Tings Wang

Chou-Shin Jou

Der-Tsyr Fan

Chon-Shin Jou

Tsai-Sen Lin

Chung-Shih Tsai

Lin Tsai-Sen

Bor-Shiun Wu

Chin-Kang Li

Jyh-Min Tsaur

Der-Tgyr Fan

A flash memory cell is provided. The flash memory cell includes a substrate having a source and a drain formed therein, a bit line contact formed above the drain, a control gate formed above the substrate, a spacer floating gate formed above the substrate and adjacent to the control gate, and a first spacer formed between the bit line contact and the control gate, wherein the first spacer is in contact with both the bit line contact and the control gate.

Structure of a non-volatile memory cell and method of forming the same

The present invention relates to a monitor method for quality of metal Antireflection Coating (ARC) layer and, more particularly, to a fast and accurate monitor method for quality of metal ARC layer. By using of immersing a silicon wafer comprising an ARC layer into an acidic (such as a developer) or an alkalescent solution for about 200-300 seconds, according to the present invention, at weak points of the metal ARC layer there occur voids (defects) due to a Galvanic cell effect enhanced by these chemical solutions and then how many defects can be counted by a wafer defect inspector such as a KLA instrument so that quality of the metal ARC layer can be monitored by this defect number. Besides, Since the silicon wafer used as a sample for the wafer defect inspector simply comes from a production line, i.e. a developing process, rather than from other additional processing, said method allows for fast and accurately monitoring quality of the metal ARC layers.

Monitor method for quality of metal ARC (antireflection coating) layer

The present invention provides a method for controlling dopant density of a plug-shaped doped polysilicon layer formed within a plug-shaped recess to prevent the dopant contained in the plug-shaped doped polysilicon layer from diffusing into a conductive layer under the plug-shaped recess through a bottom side of the plug-shaped recess, the plug-shaped recess being formed within a dielectric layer which is positioned above the conductive layer, the method comprising: (1) forming an undoped silicon layer on the surface of the plug-shaped recess; (2) forming a doped polysilicon layer on top of the undoped silicon layer to fill the plug-shaped recess; and (3) performing a thermal treatment to the semiconductor wafer so as to make the doped poly-silicon layer interact with the undoped silicon layer inside the plug-shaped recess which forms a completely doped polysilicon layer within the plug-shaped recess.

Method for controlling dopant diffusion in a plug-shaped doped polysilicon layer on a semiconductor wafer

The present invention provides a method for preventing corrosion of an aluminum-containing metallic layer having a plurality of trenches on the surface of a semiconductor chip caused by chlorine atoms residing on side walls of the trenches of the metallic layer after a trench etching process. The method comprises the following steps: (1) removing the photo resistance layer on top of the metallic layer by ashing at temperatures between 178.degree. C. and 200.degree. C. after a trench etching process, (2) using an acidic solution comprising hydroxylamine (NH.sub.2 OH), hydroquinone C.sub.6 H.sub.4 (OH).sub.2, monoethanolanine (HOCH.sub.2 CH.sub.2 NH.sub.2) and water to wash off residues on the surface of the semiconductor chip, and (3) heating the semiconductor chip for a predetermined time period at temperatures between 200.degree. C. and 250.degree. C. so as to completely dissipate the chlorine atoms resided on the side walls of the metallic layer for preventing recurrent corrosion of an aluminum-containing metallic layer.

Method for preventing corrosion of a metallic layer of a semiconductor

A trenched stack-capacitor applied in a memory unit is formed through a simple process of manufacturing a stack capacitor with high density. The process includes steps of: a) forming a contact window in the insulator for exposing a cell contact of the device; b) forming a first conducting layer over the insulator and on side-walls and a base of the contact window; c) forming an etching sacrificial layer over the first conducting layer and in the contact window; d) forming an etching masking layer over a portion of the etching sacrificial layer; e) forming a plural cylindrical etching sacrificial areas by removing an another portion of the etching sacrificial layer while retaining the etching sacrificial layer under the etching masking layer; f) forming a second conducting layer on the top of the etching masking layer, on side walls of the plural cylindrical etching sacrificial areas, over the first conducting layer and in the contact window; g) removing the plural cylindrical etching sacrificial areas while retaining the first conducting layer and the second conducting layer to form a first capacitor plate; h) forming a dielectric layer on the top of the first conducting layer and on the top and side walls of the second conducting layer; and i) forming a third conducting layer over the dielectric layer to serve as a second capacitor plate.

Growing community of inventors

Hsin-Chu, Taiwan

Tings Wang