Micron Technology Incorporated

Via Technologies, Inc.

Tingjun Xie

Zhenming Zhou

Zhenlei Shen

Jiangli Zhu

Zhengang Chen

Murong Lang

Charles See Yeung Kwong

Ying Yu Tai

Seungjune Jeon

Zhongguang Xu

Fangfang Zhu

Wei Wang

Jian Huang

Frederick Adi

Charles S Kwong

Yang Liu

Yang Lu

Juane Li

Chih-Kuo Kao

Sai Krishna Mylavarapu

Naveen Bolisetty

Nagendra Prasad Ganesh Rao

Aaron Lee

Sead Zildzic, Jr

Sead Zildzic

Steven M Pope

A processing device in a memory sub-system traverses a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit of the plurality of management units, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device. A non-transitory computer readable medium includes program instructions that when executed by a processing device, cause the processing device to perform operations of traversing a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device.

Efficient periodic backend refresh reads for reducing bit error rate in memory devices

Methods, apparatuses and systems related to managing read levels across multiple groupings or decks are described. The apparatus may include a read level management mechanism configured to controls or dynamically adjusts the read levels for the different groupings according to a real-time condition/measure associated with the programming delays.

Apparatus with multi-deck read level management and methods for operating the same

A processing device in a memory sub-system logically closes a block of a memory device to prevent additional program operations from being performed on the block. The processing device further causes one or more wordlines of the block to be programmed with padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was logically closed. In addition, the processing device causes a remaining set of wordlines of the block to be concurrently programmed to a single program state.

Partial block handling protocol in a non-volatile memory device

In some implementations, a memory device may detect a first read failure associated with a page type and a memory section of the memory device. The memory device may perform multiple read recovery operations in a first order defined by a first sequence of read recovery operations. The memory device may identify a read recovery operation that results in successful recovery from the first read failure. The memory device may reorder the first sequence of read recovery operations to generate a second sequence of read recovery operations that prioritizes the read recovery operation. The memory device may detect a second read failure associated with the page type and the memory section. The memory device may perform one or more read recovery operations to recover from the second read failure in a second order defined by the second sequence of read recovery operations.

Prioritization of successful read recovery operations for a memory device

A plurality of memory device life metrics are determined, where one of the plurality of memory device life metrics comprises a read count metric that specifies a number of read operations performed on the memory device. A plurality of normalized metric values are calculated, where each of the normalized metric values is based on a ratio of a respective memory device life metric to a respective lifetime target value associated with the respective memory device life metric. A normalized metric value that satisfies a selection criterion is identified from the plurality of normalized metric values. The identified normalized metric value corresponds to an amount of used device life of the memory device. An amount of remaining device life of the memory device is determined based on the identified normalized metric value. An indication of the amount of remaining device life is provided to a host system.

Monitoring memory device health according to data storage metrics

A processing device in a memory sub-system performs a first media scan operation with respect to a plurality of memory pages addressable by the ordinary wordline, wherein each page of the plurality of memory pages is contained by a respective management unit, and responsive to determining that a value of a data state metric of a memory page of the plurality of memory page addressable by the ordinary wordline satisfies a specified condition, performs a first media management operation with respect to a management unit containing the memory page. The processing device further performs a second media scan operation with respect to a plurality of memory pages addressable by the mandatory wordline, wherein each page of the plurality of memory pages is contained by the respective management unit, and responsive to determining that a value of the data state metric of a memory page of the plurality of memory page addressable by the mandatory wordline satisfies the specified condition, performs a second media management operation with respect to the management unit containing the memory page.

Reducing bit error rate in memory devices

A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.

Managing the programming of an open translation unit

A request to perform a memory access operation on a plurality of memory cells of a memory device is received. In response to determining that the request is from a host, a first error recovery operation is performed, wherein the first error recovery operation is associated with a first plurality of demarcation voltages. In response to determining that the request is from a controller, a second error recovery operation is performed, wherein the second error recovery operation is associated with a second plurality of demarcation voltages, wherein the second plurality of demarcation voltages comprises a greater number of demarcation voltages than the first plurality of demarcation voltages.

Managing a hybrid error recovery process in a memory sub-system

It is determined whether a write disturb capability associated with a first location of a memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of memory units is remapped to a second location of the memory device, wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.

Eliminating write disturb for system metadata in a memory sub-system

A method includes performing, over a time period, a quantity of write operations associated with a quad-level cell (QLC) memory block, determining the time period exceeds a threshold time, designating the QLC memory block as a bimodal, determining a voltage threshold level of a last successful read operation associated with the QLC memory block, and setting a read threshold level of at least a portion of the QLC memory block at the voltage threshold level of the last successful read operation.

Memory cell voltage level selection

A request to write data at a memory device is received. Responsive to receiving the request to write the data at the memory device, a first random value and a second random value is determined. Responsive to determining that the first random value does not satisfy a first threshold criterion and the second random value does not satisfy a second threshold criterion, a first write operation mode is selected from a plurality of write operations modes, and a write operation to write the data at the memory device is performed in accordance with the first write operation mode.

Selecting a write operation mode from multiple write operation modes

A processing device in a memory sub-system initiates read operations on each of a plurality of segments in a first region of the memory device during a first time interval, wherein at least a subset of the plurality of segments in the first region of the memory device are storing host data. The processing device further receives, as a result of at least one read operation, at least one data signal from a corresponding one of the plurality of segments in the first region of the memory device, and performs a signal calibration operation using the at least one data signal to synchronize one or more relevant signals with a reference clock signal used by the processing device.

Read refresh via signal calibration for non-volatile memories

A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device. The block includes a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to concurrently program a remaining set of the plurality of wordlines of the block to a threshold voltage.

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, determining that a value of a write counter associated with the memory device satisfies a first threshold criterion, wherein the write counter is a global counter indicating a number of write operations to the memory device. The operations performed by the processing device further include determining that a set of failed bit count statistics corresponding to a plurality of codewords of a memory unit satisfies a second threshold criterion. The operations performed by the processing device further include, responsive to determining that the set of failed bit count statistics corresponding to the plurality of codewords of the memory unit satisfies the second threshold criterion, performing a write scrub operation on the memory unit.

Managing write disturb for units of memory in a memory sub-system

A system includes a memory device having a plurality of memory dies and at least a first spare memory die and a processing device coupled to the memory device. The processing device is to perform operations including: tracking a value of a write counter representing a number of write operations performed at the plurality of memory dies; activating the first spare memory die in response to detecting a failure of a first memory die of the plurality of memory dies; storing an offset value of the write counter in response to activating the first spare memory die; and commanding the memory device to modify die trim settings of the first spare memory die at predetermined check point values of the write counter that are offset from the offset value.

Growing community of inventors

Milpitas, CA, United States of America

Tingjun Xie