Newport Fab, LLC

Mattson Technology, Inc

Beijing E-town Semiconductor Technology, Co., Ltd

Cypress Semiconductor Corporation

Tinghao Frank Wang

David J Howard

Dieter Dornisch

Hadi H Abdul-Ridha

Julia M Wu

Shawming Ma

Usha Raghuram

James E Nulty

Martin L Zucker

Rao Annapragada

Linda N Marquez

Kenneth M Ring

Oliver D Jan

Fen Dai

Guangming Li

Cecilia Laura Quinteros

Moo-Hyun Kim

Steven M Kennedy

Zhongming Liu

Apparatus, systems, and methods for conducting a hardmask (e.g., carbon containing hardmask) removal process on a workpiece are provided. In one example implementation, a process can include admitting a process gas into a plasma chamber, generating a plasma in the plasma chamber from the process gas using an inductively coupled plasma source, and exposing the carbon containing hardmask to the plasma to remove at least a portion of the carbon containing hardmask. The process gas can include a sulfur containing gas. The process gas does not include a halogen containing gas. The inductively coupled plasma source can be separated from the plasma chamber by a grounded electrostatic shield to reduce capacitive coupling between the inductively coupled plasma source and the plasma.

Carbon containing hardmask removal process using sulfur containing process gas

Pedestal assemblies for processing apparatus, such as plasma processing apparatus are provided. In one example implementation, a plasma processing apparatus can include a processing chamber having a processing chamber interior. The apparatus can include a plasma source configured to induce a plasma in the processing chamber interior. The apparatus can include a pedestal configured to support a substrate in the processing chamber interior during processing of the substrate. The apparatus can include a focus ring configured to be disposed around a periphery of the substrate when the substrate is supported on the pedestal. The focus ring can have a plurality of uniformly spaced apart slots. Each slot can be configured to engage with a corresponding protrusion located on the pedestal.

Pedestal assembly for plasma processing apparatus

Methods for forming microlenses on a semiconductor substrate are provided. An inductively coupled plasma etch process using a process gas that includes a mixture of CFand CHFcan be used to modify the lens shape of a plurality of microlens objects located on a semiconductor substrate to meet microlens specifications in terms of curvature, height, length, shape, and/or distance between adjacent microlens objects on the substrate. The inductively coupled plasma process can be performed in an inductively coupled plasma processing apparatus that includes a grounded Faraday shield to prevent any capacitive coupling during the plasma etching process to reduce sputtering of the microlens surface.

Methods for forming microlenses

A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.

Densely packed metal segments patterned in a semiconductor die

According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12.5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2.0 fF/um.

Method for fabricating a MIM capacitor having increased capacitance density and related structure

Method for patterning densely packed metal segments in a semiconductor die and related structure

Prior to etching a poly-II layer during fabrication of an integrated circuit, a hydrofluoric acid (HF) dip is used to remove surface oxides from the poly-silicon layer and an anisotropic descumming operation is used to remove any resist material left over from a patterning operation. Following patterning, a long breakthrough etch (e.g., sufficient to remove 300-1500 &#x212b; of oxide) using an anisotropic breakthrough etchant (e.g., a fluorocarbon-based etchant) is performed before the poly-silicon layer is etched. The HF dip may be repeated if a predetermined time between the first dip and the etch is exceeded. The anisotropic descumming operation may be performed using an anisotropic anti-reflective coating (ARC) etch, e.g., a Cl/O, HBr/O, CF/Oor another etch having an etch rate of approximately 3000 &#x212b;/min for approximately 10-20 seconds. The poly-silicon layer may be annealed following (but not prior to) the etch thereof.

Method for etching and/or patterning a silicon-containing layer

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Irvine, CA, United States of America

Tinghao Frank Wang