Promos Technologies, Inc

Mosel Vitelic Corporation

Ting Sing Wang

Der-Tsyr Fan

Chon-Shin Jou

Ya Ling Po

John Chu

Meng Fen Cheng

A multi-step gate structure comprises a semiconductor substrate having a multi-step structure, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the gate oxide layer has different thicknesses on each step surface of the multi-step structure. In addition, the multi-step gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure. The channel length of the multi-step gate structure is the summation of the lateral width and the vertical depth of the multi-step gate structure, which is dramatically increased such that problems originated from the short channel effect can be effectively solved. Further, the plurality of doped regions under the multi-step structure are prepared by implanting processes having different dosages and dopants, which can control the thickness of the gate oxide layer and the threshold voltage of the multi-step gate structure.

Multi-step gate structure and method for preparing the same

A recessed gate structure comprises a semiconductor substrate, a recess positioned in the semiconductor substrate, a gate oxide layer positioned in the recess and a conductive layer positioned on the gate oxide layer, wherein the semiconductor substrate has a multi-step structure in the recess. The thickness of the gate oxide layer on one step surface can be different from that on another step surface of the multi-step structure. In addition, the recessed gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure, and these doped regions may use different dosages and different types of dopants. There is a carrier channel in the semiconductor substrate under the recessed gate structure and the overall channel length of the carrier channel is substantially the summation of the lateral width and twice of the vertical depth of the recessed gate structure.

Recessed gate structure and method for preparing the same

A dynamic random access memory structure having a vertical floating body cell includes a semiconductor substrate having a plurality of cylindrical pillars, an upper conductive region positioned on a top portion of the cylindrical pillar, a body positioned below the upper conductive portion in the cylindrical pillar, a bottom conductive portion positioned below the body in the cylindrical pillar, a gate oxide layer surrounding the sidewall of the cylindrical pillar and a gate structure surrounding the gate oxide layer. The upper conductive region serves as a drain electrode, the bottom conductive region serves as a source electrode and the body can store carriers such as holes. Preferably, the dynamic random access memory structure further comprises a conductive layer positioned on the surface of the semiconductor substrate to electrically connect the bottom conductive regions in the cylindrical pillars.

Dynamic random access memory structure

The method for preparing a deep trench uses a dry etching process to form a trench in a silicon substrate, and an etching mixture is then coated on the surface of the silicon substrate and inside the deep trench. A portion of etching mixture is removed from the surface of the silicon substrate and the trench above a predetermined depth from the surface of the substrate, and an etching process is then performed using the etching mixture remaining inside the trench to etch the silicon substrate below the predetermined depth so as to form the deep trench. The etching mixture comprises a conveying solution and an etchant, and the viscosity of the conveying solution is higher than that of the etchant. The conveying solution is spin-on-glass or a photoresist, and the etchant is tetramethylammonium hydroxide, ammonium, or hydrofluoric acid. The volume ratio of the conveying solution and the etchant is preferably between 50:1 and 20:1.

Method for preparing a deep trench and an etching mixture for the same

A method for manufacturing a semiconductor device having an excellent metallization is provided. The method includes the steps of a). providing a semiconductor substrate, b) forming a conductive layer on the semiconductor substrate, c) forming a dielectric layer on the conductive layer, d) forming a titanium nitride layer directly on the dielectric layer without contacting the conductive layer, and e) patternizing the titanium nitride layer, the dielectric layer and the conductive layer, wherein the dielectric layer is used for avoiding spontaneous electrochemical reaction between the titanium nitride layer and the conductive layer,

Metallizing process of semiconductor industry

The present invention is a method for increasing the refresh time of DRAM. This invention is for decreasing the stress between the bird's beak of field oxide and silicon substrate by using fluorine ion implant before field oxidation and the optimal structure of LOCOS to effectively preventing the current leakage from the bird's beak of field oxide. Therefore, this invention can increase the refresh time of DRAM and greatly enhance the performance in DRAM.

Growing community of inventors

Hsinchu, Taiwan

Ting Sing Wang