Powertech Technology Inc.

Ting-Feng Su

Chia-Jen Chou

Chien-Ming Chen

Chi-Liang Pan

A semiconductor device package has a die, a pattern of dielectric material formed on an active surface of the die, a plurality of metal contacts electrically connected to the die and surrounded by the pattern, a mold compound formed around the pattern, the die and the metal contacts, and a redistribution layer formed on a grinded surface of the mold compound and electrically connected to the metal contacts. The dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound.

Semiconductor device package with a stress relax pattern

A chip structure including a chip and a redistribution layer is provided. The chip includes a plurality of pads. The redistribution layer includes a dielectric layer and a plurality of conductive traces. The dielectric layer is disposed on the chip and has a plurality of contact windows located above the pads. The conductive traces are located on the dielectric layer and are electrically coupled to the pads through the contact windows. At least one of the conductive traces includes a body and at least one protrusion coupled to the body, and the at least one protrusion is coupled to an area of the body other than where the contact windows are coupled to on the body.

Chip structure having redistribution layer

A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.

Fan-out wafer level package structure

A multi-chip stacked package primarily comprises a chip carrier, a first chip disposed on the chip carrier, a plurality of die-attaching bars, a second chip stacked on the first chip by the adhesion of the die-attaching bars, and a plurality of bonding wires electrically connecting the first chip to the chip carrier. The die-attaching bars are formed on the first chip in a specific pattern and have an adhesive surface away from the first chip for adhering the second chip. The bonding wires have a loop height lower than the adhesive surface in a manner that specific sections of the bonding wires are embedded in the corresponding die-attaching bar from the adhesive surface. Accordingly, the die-attaching bars can modify and fasten the bonding wires in advance to avoid collapse and deformation of the bonding wires during stacking of the second chip and encapsulating processes.

Multi-chip stacked package

An apparatus for drop testing is disclosed. The apparatus has a drop angle setting jig that horizontally moves on a support frame and positions a test object at a predetermined angle by clamping with a fixture. The jig provides a second datum plane and is connected to a moveable holding frame, with the holding frame providing a first datum plane. After the fixture clamps the testing object, the jig can be pulled back without touching the testing object, and the testing object stays still. Therefore, the testing object can be precisely positioned. Furthermore, with the sliding track and the stopping block, the jig is able to quickly return back to the reference position.

Growing community of inventors

Hsinchu County, Taiwan

Ting-Feng Su