Intel Corporation

Advanced Technology Materials, Inc.

Other

Timothy E Glassman

Hui Jae Yoo

Sean W King

Sreenivas Kosaraju

Thomas H Baum

Peter S Kirlin

Brian A Vaartstra

Robin A Gardiner

Douglas J Gordon

Matthew V Metz

Oleg Golonzka

Nick Lindert

Nathan Strutt

Dragos Seghete

Sofia Pombrik

Namrata S Asuri

Robert S Chau

W Karl Olander

Gautam Bhandari

Hiten Kothari

Christopher G Parker

Matthew J Andrus

Connie L Gordon, Legal Representative

Mark L Doczy

Suman Datta

Justin K Brask

Christopher J Jezewski

Scott A Hareland

Reza Arghavani

Christopher J Wiegand

Michael A Todd

James V McManus

Joseph M Steigerwald

Markus Kuhn

Steven J Keating

Ying Zhou

Sunit Tyagi

Daniel Ouellette

Douglas W Barlage

Andre Baran

Paul V Chayka

Douglas Cameron Gordon

Lawrence Foley

Sophia Pombrik

Brian A Vaastra

Patrick J Hentges

Trinh T Van

Ameya S Chaudhari

Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.

Conformal low temperature hermetic dielectric diffusion barriers

An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.

Resistive random access memory device and methods of fabrication

A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.

Resistive random access memory device with switching multi-layer stack and methods of fabrication

Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.

RRAM devices with reduced forming voltage

Metal-insulator-metal (MIM) capacitors with insulator stacks having a plurality of metal oxide layers are described. For example, a MIM capacitor for a semiconductor device includes a trench disposed in a dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. An insulator stack is disposed above and conformal with the first metal plate. The insulator stack includes a first metal oxide layer having a first dielectric constant and a second metal oxide layer having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant. The MIM capacitor also includes a second metal plate disposed above and conformal with the insulator stack.

Metal-insulator-metal (MIM) capacitor with insulator stack having a plurality of metal oxide layers

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Portland, OR, United States of America

Timothy E Glassman