International Business Machines Corporation

Globalfoundries Inc.

Timothy Charles Krywanczyk

Steven Ross Codding

Donald W Brouillette

Matthew R Whalen

Edmund Juris Sprogis

Matthew T Tiersch

Joseph D Danaher

Eric Jeffrey White

S Jay Chey

Lawrence D David

Cornelia Kang-I Tsang

Timothy E Neary

Mohammed S Shaikh

Amye L Wells

Jerome Brett Lasky

Paul M Feeney

Joseph R Greco

Rick L Mohler

Jose L Cruz

Douglas Keith Sturtevant

David Domina

Allan D Abrams

James L Hardy, Jr

Ivan J Stone

Steven A Martel

Wolfgang Otto Rauscher

Rene A Lamothe

Wolfgang Sauter

Rosemary A Previti-Kelly

David Michael Audette

Cuc Kim Huynh

David C Thomas

Matthew D Moon

Paul H Smith, Jr

John Chester Malinowski

Scott Alan Estes

Rock Nadeau

Jason P Ritter

Joel M Sharrow

Damyon L Corbin

Brian Douglas Pfeifer

Kenneth H Yao

John C Hall

Caitlin W Weinstein

Dean Allen Schaffer

James R Palmer

Erik M Probstfield

Robert R Cadieux

Patrick A Raymond

Melvin T Kelly

Chad R Binkerd

James R Johnson

Patricia Schink

Clark D Reynolds

Steven G Perrotte

Michael S Lube

Thomas F Curran, Jr

Brian J Thibault

Jocelyn Sylvestre

The present disclosure relates to semiconductor structures and, more particularly, to a method to control depth of etch in deep via etching and related structures. The method includes: forming an interface within the substrate between an etch control dopant and material of the substrate; etching a via within substrate; and terminating the etching of the via at the interface upon detection of the interface.

Controlling of etch depth in deep via etching processes and resultant structures

A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.

Silicon chicklet pedestal

There is provided a UV energy curable tape comprising an adhesive material including a UV energy curable oligomer, a UV energy initiator, and a material which emits optical light when the tape composition is substantially fully cured. A semiconductor chip made using the tape is also provided.

Ultraviolet energy curable tape and method of making a semiconductor chip using the tape

Disclosed are embodiments of a method of removing patterned circuit structures from the surface of a semiconductor wafer. The method embodiments comprise blasting the surface of the semiconductor wafer with particles so as to remove substantially all of the patterned circuit structures. The blasting process is followed by one or more grinding, polishing and/or cleaning processes to remove any remaining circuit structures, to remove any lattice damage and/or to achieve a desired smoothness across the surface of the semiconductor wafer.

Method to recover patterned semiconductor wafers for rework

Method of forming silicon chicklet pedestal

A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical support to enable thinning of the semiconductor substrate to a thickness of about 25 &#x3bc;m. A film frame tape is attached to the back side of the thinned semiconductor substrate and the laser-ablative adhesive layer is ablated by laser, thereby dissociating the carrier substrate from the back side of the C4 grind tape. The assembly of the film frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. The C4 grind tape is irradiated by ultraviolet light to become less adhesive, and is subsequently removed.

Method of thinning a semiconductor substrate

An improved method of dicing a semiconductor wafer which substantially reduces or eliminates corrosion of copper-containing, aluminum bonding pads. The method involves continuously contacting the bonding pads with deionized water and an effective amount of a copper corrosion inhibiting agent, most preferably benzotriazole. Also disclosed, is an improved apparatus for dicing a wafer, in which a copper corrosion inhibiting agent is included in the cooling system for cooling the dicing blade.

Corrosion inhibitor additives to prevent semiconductor device bond-pad corrosion during wafer dicing operations

A method for inspecting a semiconductor wafer fabricated for image sensing operation that has had a transparent protective tape layer applied to a front or active wafer surface. The method includes quantifying chip defects in the image sensor wafer that lie under the protective layer using automatic disposition equipment.

Inspection method for protecting image sensor devices with front surface protection

A method for preventing edge chipping and cracking damage encountered by semiconductor chips in a die picking operation during separation from an adhesive sheet. Also provided is a device for preventing potential edge chipping and cracking damage encountered by a semiconductor chip during die picking processes.

Methods to prevent ECC (edge chipping and cracking) damage during die picking process

A method of recycling monitor wafers. The method includes: (a) providing a semiconductor wafer which includes a dopant layer extending from a top surface of the wafer into the wafer a distance less than a thickness of the wafer, the dopant layer containing dopant species; after (a), (b) attaching an adhesive tape to a bottom surface of the wafer; after (b), (c) removing the dopant layer; and after (c), (d) removing the adhesive tape.

Method for recycling of ion implantation monitor wafers

In accordance with the foregoing objects and advantages, the present invention provides a fabrication device that may be used during the grinding operation of the fabrication process. The fabrication device comprises a socket plate that includes a plurality of cavities formed therein that correspond in position and number to the solder (or other conductive material) bumps formed on the front surface of a product wafer.

System and device for thinning wafers that have contact bumps

A wafer processing method. The method includes providing a semiconductor wafer. The semiconductor wafer includes (i) a semiconductor layer and (ii) a dopant layer on top of the semiconductor layer. The dopant layer comprises dopants. The method further includes removing the dopant layer from the semiconductor wafer. No chemical etching is performed on the dopant layer before said removing the dopant layer is performed.

Recycling of ion implantation monitor wafers

Growing community of inventors

Essex Junction, VT, United States of America

Timothy Charles Krywanczyk