Micron Technology Incorporated

Other

Tim J Corbett

Alan G Wood

Warren M Farnworth

Fernando N Gonzalez

Raymond P Scholer

Larry Duane Kinsman

Chender Huang

Gary L Chadwick

Walter L Moden

Trung Tri Doan

Xiao Li

Sameer S Vadhavkar

Magnetically adjusting color-converting particles within a matrix and associated devices, systems, and methods are disclosed herein. A magnetic-adjustment process can include applying a magnetic field to a mixture including a non-solid matrix and a plurality of color-converting particles (e.g. magnetically anisotropic color-converting particles). The magnetic field can cause the plurality of color-converting particles to move into a generally non-random alignment (e.g., a generally non-random magnetic alignment and/or a generally non-random shape alignment) within the non-solid matrix. The non-solid matrix then can be solidified to form a solid matrix. A magnetic-adjustment process can be performed in conjunction with testing and/or product binning of solid-state radiation transducer devices. For example, a position, direction, strength, or duration of a magnetic field used to perform a magnetic-adjustment process can be controlled according to optical output collected from a solid-state radiation transducer device. Measuring the optical output and performing the magnetic-adjustment process can be at least partially concurrent.

Magnetically adjusting color-converting materials within a matrix and associated devices, systems, and methods

A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness to form a thinned substrate; applying a dopant to the back side of the thinned substrate; and laser processing the back side of the thinned substrate to form a plurality of patterns of lasered features containing the dopant. The dopant can be selected to modify properties of the semiconductor substrate such as carrier properties, gettering properties, mechanical properties or visual properties.

Method for fabricating semiconductor components having lasered features containing dopants

A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate.

Thinned semiconductor components having lasered features and method of fabrication

A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness; laser processing the back side of the thinned substrate to form at least one lasered feature on the back side; and dicing the substrate into a plurality of components having the lasered feature. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate. A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate.

Methods for fabricating semiconductor components using thinning and back side laser processing

A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Universal wafer carrier for wafer level die burn-in

A laser marking apparatus and method for marking the surface of a semiconductor chip are described herein. A laser beam is directed to a location on the surface of the chip where a laser-reactive marking material, such as a pigment containing epoxy, is present. The heat associated with the laser beam causes the laser-reactive marking material to fuse to the surface of the chip, creating a visibly distinct mark in contrast to the rest of the surface of the chip. Only reactive material contacted by the laser fuses to the chip surface and the remaining residue on the non-irradiated portion can be readily removed.

Comparing identifying indicia formed using laser marking techniques to an identifying indicia model

A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Method for testing using a universal wafer carrier for wafer level die burn-in

A reusable burn-in/test fixture for discrete TAB die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. When the two halves are assembled, the fixture establishes electrical contact with the die and with a burn-in oven. The test fixture need not be opened until the burn-in and electrical test are completed. The fixture permits the die to be characterized prior to assembly.

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Boise, ID, United States of America

Tim J Corbett