Infineon Technologies Ag

Siemens Aktiengesellschaft

Till Schl&ouml;sser

Franz Hofmann

Josef Willer

Wolfgang Krautschneider

Thomas Peter Haneder

Werner Weber

Alexander Frey

Gerrit Lange

Bernhard Sell

Roland Thewes

Georg Braun

Lothar Risch

Franz Kreupl

Emmerich Bertagnolli

Dirk Manger

Volker Weinrich

Richard Johannes Luyken

Dietmar Gogl

Thomas B&ouml;hm

Armin Kohlhase

Wolfgang R&ouml;sner

Wolfgang H&ouml;nlein

Andreas Rusch

Manfred Hain

Gerhard M&uuml;ller

Yoichi Otani

Franz Hoffmann

Thomas-Peter Haneder

Paul-Werner Basse

As a consequence of DRAM memory cell miniaturization, the available space for read/write amplifiers decreases in width from hitherto 4 bit line grids to 2 bit lines grids. Conventionally previously known read/write amplifiers cannot be accommodated on this reduced, still available space. Therefore, it has not been possible hitherto to provide read/write amplifiers arranged beside one another which would manage with the novel DRAM memory cell spacings. The principle underlying the invention is based on replacing at least some of the transistors of conventional design which are usually used for read/write circuits by &ldquo;vertical transistors&rdquo; in which the differently doped regions are arranged one above the other or practically one above the other. Compared with the use of conventional transistors, the use of vertical transistors saves enough space to ensure an arrangement of a read/write circuit in the grid even with a reduced grid width.

Read/write amplifier having vertical transistors for a DRAM memory

A field-effect transistor that having a nanowire, which forms a source region, a channel region and a drain region of the field-effect transistor, the nanowire being a semiconducting and/or metallically conductive nanowire. The field-effect transistor also has at least one nanotube, which forms a gate region of the field-effect transistor, the nanotube being a semiconducting and/or metallically conductive nanotube. The nanowire and the nanotube are arranged at a distance from one another or set up in such a manner that it is substantially impossible for there to be a tunneling current between the nanowire and the nanotube, and that the conductivity of the channel region of the nanowire can be controlled by means of a field effect as a result of an electric voltage being applied to the nanotube.

Field effect transistor

An integrated memory with a configuration of non-volatile memory cells based on ferromagnetic storage contains both powerful memory cells with a magnetoresistive effect with a transistor control and cost-effective memory cells with a magnetoresistive effect with memory elements connected between the word lines and bit lines. The memory elements connected directly between the bit line and the word line are preferably inserted in memory cell arrays that can be stacked one above the other above the memory cells with the transistor, and thereby achieve a high integration density. The fact that the memory, which contains both types and thereby satisfies all the system requirements, is fabricated in one module and in one process sequence considerably lowers the fabrication costs.

Integrated memory with a configuration of non-volatile memory cells and method for fabricating and for operating the integrated memory

In semiconductor memories having a surrounding gate configuration, webs, i.e. vertical rectangular pillars made of substrate material, are formed at the surface of a semiconductor substrate and are surrounded by the gate electrodes in a lower region. Conventionally, it is not possible for word lines to make contact with the gate electrodes in the lower region of the webs without at the same time electrically influencing substrate regions at a higher level in the webs or short-circuiting bit lines from their sidewalls, unless complicated methods requiring additional lithography steps are used. A method for the self-aligning, selective contact-connection of the peripheral gate electrodes is performed with the aid of an insulation layer having a smaller layer thickness than the peripheral gate electrodes.

Integrated semiconductor memory and fabrication method

The present invention relates to a FEMFET device with a semiconductor substrate and to at least one field effect transistor that is provided in the semiconductor substrate. The field effect transistor has a source area, a drain area, a channel area and a gate stack. The gate stack has at least one ferroelectric layer and at least one thin diffusion barrier layer being arranged between the lowest ferroelectric layer and the semiconductor substrate and being configured in such a way that an out-diffusion of the components of the ferroelectric layer into the semiconductor substrate is essentially prevented.

FEMFET device and method for producing same

To simplify a method for manufacturing a memory device having a multiplicity of MRAM cells in a crossing area of conductor elements, a method for manufacturing a semiconductor circuit system, in particular, a memory device or the like, having a plurality of memory cells includes the step of structuring each of the memory elements simultaneously with the structuring of the first and second conductor elements.

Method for manufacturing a semiconductor circuit system

A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface made of tungsten silicide placed on a tungsten silicide layer which is disposed near a surface of a electrode body. The graining of the tungsten silicide layer is formed by tempering a temporarily present double layer that is formed of an understoichiometric tungsten silicide layer and a silicon layer. The double layer is formed on the tungsten silicide layer.

Miniaturized capacitor with solid-state dielectric, in particular for integrated semiconductor memories, E.G. DRAMS, and method for fabricating such a capacitor

The method of the invention, in contrast to conventional trench capacitors wherein the memory node is formed in a trench, normally in the form of a drilled hole, includes the steps of forming the memory node in the monocrystalline silicon of the substrate and remains as a web during an etching process while a trench is filled with the common opposing electrode of the memory cell array. In the method, it is advantageous for the selection transistor to be in the form of a vertical transistor above the memory node in the freestanding web.

Method for producing a memory cell for a semiconductor memory

A depression extends from a main surface of the substrate to the inside of said substrate and has an upper area and an adjacent lower area. A cross-section of the upper area, parallel to the main surface, is provided with at least one corner. A cross-section of the lower area, parallel to the main surface, matches the cross-section of the upper area, particularly in the vicinity the upper area, with the following difference: each corner is rounded, whereby the cross section of the lower area is smaller than the cross-section of the upper area. In order to produce the indentation, the upper area is provided with an auxiliary spacer that is rounded by isotropic etching. The lower area is produced by selectively etching the substrate to form an auxiliary spacer.

Substrate assembly having a depression suitable for an integrated circuit configuration and method for its fabrication

An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.

Integrated circuit configuration and method for manufacturing it

DRAM cell arrangement and method for fabricating it Word lines and bit lines are arranged above a main area of a substrate, with the result that they have a planar construction and can be produced together with gate electrodes of transistors of a periphery of the cell arrangement. A depression of the substrate is provided per memory cell, a storage node of a storage capacitor being arranged in the lower region of said depression and a gate electrode of a vertical transistor being arranged in the upper region of said depression. The depressions of the memory cells are arranged between trenches filled with isolating structures. Upper source/drain regions of the transistors are arranged between two mutually adjacent isolating structures and between two mutually adjacent depressions. Lower source/drain regions are arranged in the substrate and adjoin the storage nodes. For process steps, alignment tolerances are so large that the space requirement for the memory cell can amount to 4F .

DRAM cell system and method for producing same

The process first forms trench capacitors in a substrate, which are filled with a trench fill and in which a first insulating layer is disposed over the conductive trench fill. The first insulating layer is then overgrown laterally by a selectively grown epitaxial layer. The selective epitaxial layer is so structured that a ridge is formed from it. Next, the ridge is partially undercut, whereby the etch selectivity of the ridge relative to the first insulating layer is utilized for a wet-chemical etching procedure. Next, a contact layer is arranged in the undercut region, which connects the ridge and a transistor that has been formed in the ridge to the conductive trench fill. Lateral margin ridges are then formed next to the ridge as a gate, and a doped region is incorporated into the ridge as a source/drain zone of the transistor.

Method for producing a cell of a semiconductor memory

A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic intermediate layer is disposed on the surface of the channel region and forms a Schottky diode with the semiconductor substrate, and a ferroelectric layer and a gate electrode are disposed on its surface. The ferroelectric transistor is fabricated using steps appertaining to silicon process technology.

Ferroelectric transistor and method for fabricating it

An integrated dynamic memory cell having a small area of extent on a semiconductor substrate is described. The memory cell has a selection MOSFET with a gate connection area that is connected to a word line, a source connection doping area which is connected to a bit line, and a drain connection doping area. A memory MOSFET has a gate connection area which is connected via a thin dielectric layer to a connection doping region which connects a source connection doping area of the memory MOSFET to the drain connection doping area of the selection MOSFET. The memory MOSFET further has a drain connection doping area that is connected to a supply voltage. The selection and memory MOSFETs are disposed on opposite sidewalls of a trench, which is etched in the substrate, and the connection doping region forms a bottom of the trench.

Integrated dynamic memory cell having a small area of extent, and a method for its production

A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.

Growing community of inventors

Dresden, Germany

Till Schlösser

Growing community of inventors

Dresden, Germany

Till Schl&ouml;sser

Till Schlösser