Intel Corporation

Tiffany Byrne

Daoqiang Lu

Eric Jin Li

Paul A Koning

Christopher L Rumer

Gudbjorg H Oskarsdottir

Edward L Martin

Darcy E Fleming

Saikumar Jayaraman

Daewoong Suh

Mitesh C Patel

Wei Keat Loh

Sheau Hooi Lim

Stephen E Lehman

Yoong Tatt P Chin

Mohd Erwan B Basiron

Carl L Deppisch

Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat formulation deposited onto a semiconductor wafer prior to the laser scribe operation. Upon removal of the wafer coat layer, the organic surface protectant remains on the bumps and thereby prevents oxidation of the bumps between die prep and chip and attach. In an alternative embodiment, an ultraviolet light absorber is added to the wafer coat formulation to enhance the wafer coat layer's energy absorption and thereby improve the laser's ability to ablate the wafer coat layer. In an alternative embodiment, a conformal wafer coat layer is deposited on the wafer and die bumps, thereby reducing wafer coat layer thickness variations that can impact the laser scribing ability.

Semiconductor wafer coat layers and methods therefor

A composition includes a solder paste matrix and a solder mixture including a tin-based solder alloy. The composition also includes a discrete dispersion of a metal. The tin-based alloy includes a melting first temperature and the metal includes a melting second temperature. The melting second temperature is greater than the melting first temperature. The discrete dispersion is in a particle range of a majority passing minus 520-mesh. A process includes blending the solder mixture and the metal under non-alloying conditions to achieve the discrete dispersion of the metal. A process includes reflowing the composition such that the composition when solidified, has a melting point that is higher than the solder mixture in the composition.

In-situ alloyed solders, articles made thereby, and processes of making same

A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.

Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same

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Chandler, AZ, United States of America

Tiffany Byrne