Taiwan Semiconductor Manufacturing Comp. Ltd.

Tien-Lu Lin

Yu-Ming Lin

Chia-Hao Chang

Chih-Hao Wang

Tai-I Yang

Jia-Chuan You

Cheng-Chi Chuang

Lin-Yu Huang

Yung-Chih Wang

Sheng-Tsung Wang

Chia-Tien Wu

Yu-Chieh Liao

Hsiang-Wei Liu

Shih-Chuan Chiu

Hsiang-Lun Kao

Tien-I Bao

Li-Zhen Yu

Chun-Yuan Chen

Jian-Hua Chen

Wai-Yi Lien

Chia-Lin Chuang

Jiun-Peng Wu

Ru-Gun Liu

Chih-Ming Lai

Jiann-Tyng Tzeng

Chih-Liang Chen

Shih-Wei Peng

Charles Chew-Yuen Young

Kam-Tou Sio

Shun Li Chen

Hui-Ting Yang

Che-Chen Wu

Kuo-Chi Tu

Chen-Jong Wang

Hsiang-Huan Lee

Jung-Hung Chang

Yung-Hsu Wu

Ta-Chun Lin

Wei-Chen Chu

Chun-Yao Chen

Jung-I Lin

Shau-Lin Shue

Kuo-Cheng Ching

Carlos H Diaz

Yeur-Luen Tu

Huan-Chieh Su

Zhi-Chang Lin

Chih-Hao Chang

Kuo-Ching Huang

Hsiao-Hui Tseng

Chung-Wei Chang

Wen-Cheng Chen

Huey-Chi Chu

Jheng-Sheng You

Tsung-Hsun Huang

Chih-Shen Yang

Chi-Fu Lin

Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.

Semiconductor device structure

A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

Semiconductor device structure and method for forming the same

A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Contact resistance between via and conductive line

A semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a gate electrode layer formed over a semiconductor substrate and capped with a conductive capping layer. The semiconductor device structure also includes an insulating capping stack having a lower surface that faces and is spaced apart from an upper surface of the conductive capping layer. In addition, the semiconductor device structure includes gate spacers formed over the semiconductor substrate and covering opposing sidewalls of the gate electrode layer, the conductive capping layer, and the insulating capping stack.

Semiconductor device with air gap on gate structure and method for forming the same

A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.

Method of fabricating semiconductor device

A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

Source/drain isolation structure and methods thereof

A semiconductor device structure is provided. The semiconductor device structure includes a contact over a source/drain region of a fin structure, a gate stack over a channel region of the fin structure, a first mask layer covering the gate stack, and a second mask layer covering the contact. A side surface of the first mask layer is direct contact with a side surface of the second mask layer, and the first mask layer includes a portion directly below the second mask layer.

Semiconductor device structure and method for forming the same preliminary class

A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.

Methods of forming contact features in field-effect transistors

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ILD) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ILD layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. The semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ILD layer and a source/drain contact to the source/drain regions disposed in the device-level ILD layer.

Semiconductor device with multi-layer dielectric and methods of forming the same

A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.

Metal line structure and method

Semiconductor device with multi-layer dielectric

A method of forming an integrated circuit structure includes forming a first source/drain contact plug over and electrically coupling to a source/drain region of a transistor, forming a first dielectric hard mask overlapping a gate stack, recessing the first source/drain contact plug to form a first recess, forming a second dielectric hard mask in the first recess, recessing an inter-layer dielectric layer to form a second recess, and forming a third dielectric hard mask in the second recess. The third dielectric hard mask contacts both the first dielectric hard mask and the second dielectric hard mask.

Slot contacts and method forming same

A method of forming a semiconductor structure includes first forming a metal gate (MG) over a semiconductor layer, a gate spacer on a sidewall of the MG, and a source/drain (S/D) feature disposed in the semiconductor layer and adjacent to the MG, forming an S/D contact (MD) over the S/D feature, forming a first ILD layer over the MG and the MD, and subsequently patterning the first ILD layer to form an opening. The method further includes forming a metal layer in the opening, such that the metal layer contacts both the MG and the MD, removing a top portion of the metal layer to form a trench, filling the trench with a dielectric layer, and subsequently forming a second ILD layer over the dielectric layer.

Butted contacts and methods of fabricating the same in semiconductor devices

The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.

Semiconductor structure with a laminated layer

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Hsinchu, Taiwan

Tien-Lu Lin