Maxim Integrated Products, Inc.

Other

Tiao Zhou

Viren V Khandekar

Arkadii V Samoilov

Yong L Xu

Karthik Thambidurai

Yi-Sheng Anthony Sun

Abhishek Choudhury

Xiansong Chen

Joseph W Serpiello

Ricky Agrawal

Md Kaysar Rahim

S Kaysar Rahim

Kaysar M Rahim

Packaging techniques are described for fabricating an sensor package that include one or more sensor devices, such as optical sensors or light sources, where an active side of the sensor device is exposed. Additionally, the side of the sensor package including the sensor die is substantially flat (e.g., topology is less than about 75 &#x3bc;m), the sensor package does not include wire bonding, and the package interconnect (e.g., solder bump array or other connection) is disposed on a side of the sensor package opposite the sensor die.

Exposed die sensor package

A device and fabrication techniques are described that employ wafer-level packaging techniques for fabricating semiconductor devices that include a pad defined contact. In implementations, the wafer-level package device that employs the techniques of the present disclosure includes a substrate, a passivation layer, a top metal contact pad, a thin film with a via formed therein, a redistribution layer structure configured to contact the top metal contact pad, and a dielectric layer on the thin film and the redistribution layer structure. In implementations, a process for fabricating the wafer-level package device that employs the techniques of the present disclosure includes processing a substrate, forming a passivation layer, depositing a top metal contact pad, forming a thin film with a via formed therein, forming a redistribution layer structure in the via formed in the thin film, and forming a dielectric layer on the thin film and the redistribution layer structure.

Pad defined contact for wafer level package

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 &#x3bc;m) and fifty micrometers (50 &#x3bc;m) from the lead. In some embodiments, the core covers between at least approximately one-third (&#x2153;) and one-half (&#xbd;) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

Solder fatigue arrest for wafer level package

Techniques are described herein for a dip soldering process which provides a low-profile, low-cost solder bump formation process which may be implemented to promote package thickness scaling (e.g., reduce the overall package thickness). For example, the dip soldering process disclosed herein may enable ultra-thin wafer-level packages (WLP), ultra-thin wafer level quad-flat no-leads (WQFN) packages, or the like.

Low-cost low-profile solder bump process for enabling ultra-thin wafer-level packaging (WLP) packages

In implementations, a glass-based multichip package includes a photodefinable glass-based substrate, at least one electronic component disposed on the photodefinable glass-based substrate, and a portion of the photodefinable glass-based substrate that has been exposed to ultraviolet light, where the portion of the photodefinable glass-based substrate includes ceramic. Additionally, the sensor package may include additional electronic components, a glass touch panel, and/or a printed circuit board. In implementations, fabricating the sensor package device includes receiving a photodefinable glass-based substrate, etching the photodefinable glass-based substrate, and forming a ceramic portion of the photodefinable glass-based substrate.

Glass based multichip package

Packaging techniques are described for fabricating a flex sensor package that includes a flex printed circuit with a flex window, an adhesive layer with an adhesive layer window, and a stiffener assembly with a stiffener window on a first side of the flex printed circuit and a semiconductor die on a second side of the flex printed circuit. In implementations, fabricating the flex sensor package includes receiving a flex printed circuit including at least one flex window, placing an adhesive layer on at least a portion of a first side of the flex printed circuit, placing a stiffener assembly on the adhesive layer, and placing at least one semiconductor die on a second side of the flex printed circuit, where an active portion of the at least one semiconductor die is aligned with the at least one flex window and the adhesive layer window.

Highly integrated flex sensor package

Semiconductor package devices, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.

Techniques for wafer-level processing of QFN packages

WLP semiconductor devices include bump assemblies that have a barrier layer for inhibiting electromigration within the bump assemblies. In an implementation, the bump assemblies include copper posts formed on the integrated circuit chips of the WLP devices. Barrier layers formed of a metal such as nickel (Ni) are provided on the outer surface of the copper posts to inhibit electromigration in the bump assembly. Oxidation prevention caps formed of a metal such as tin (Sn) are provided over the barrier layer. Solder bumps are formed over the oxidation prevention caps. The oxidation prevention caps inhibit oxidation of the barrier layer during fabrication of the bump assemblies.

Wafer level package (WLP) device having bump assemblies including a barrier metal

An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP.

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Carrollton, TX, United States of America

Tiao Zhou