International Business Machines Corporation

Thurston Bryce Youngs, Jr

Mark Vincent Pierson

Ivan I Chobot

Reinaldo Anthony Neira

John A Covert

Paul C Sviedrys

Louise A Tiemann

Gerald A Valenta

Alexander Petrovich

Donald W Miller

Keith D Mansfield

Randy L Haight

Voya Rista Markovich

Charles Gerard Woychik

John Steven Kresge

Sylvia Adae-Amoakoh

Robert A Martone

Jennifer Rebecca Sweterlitsch

Michael A Gaynes

David Brian Stone

Darleen Mayo

Robert B Conn

Kenneth L Spink, Jr

A method for forming a flip-chip joinable substrate having non-plated-on contact pads. The substrate has an external metal foil layer upon a dielectric layer upon a patterned internal metal layer having an internal contact area. An area of the external metal foil layer above the internal contact area is selected. A microvia cavity extending to the internal contact area is perforated centrally within the selected area and is filled with a mass of conductive paste forming an external contact pad. The external contact pad is used as an etch mask for removing the adjacent external metal foil.

Economical high density chip carrier

A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

Methods of making and using a floating interposer

Floating interposer

A flip-chip joinable substrate having non-plated-on contact pads. The substrate has an external metal foil layer upon a dielectric layer upon a patterned internal metal layer having an internal contact area. An area of the external metal foil layer above the internal contact area is selected. A microvia cavity extending to the internal contact area is perforated centrally within the selected area and is filled with a mass of conductive paste forming an external contact pad. The external contact pad is used as an etch mask for removing the adjacent external metal foil.

An integrated circuit package derives increased mechanical robustness and electrical reliability consistent with increased heat dissipation capacity by edge bonding of integrated circuit chips onto a substrate such as a chip, board, module or another integrated circuit by forming a solder or conductive adhesive bond between a bonding/contact pad on the substrate and a metallization feature extending at least on limited opposing areas of major surfaces of the chip and, preferably, across the edge of the chip. Thermally conducting material contained in a cap may provide additional, distributed support for the chip by a combination of viscosity and density providing buoyancy of the chips. Alternatively, a cap may be provided which further stabilizes the edge-mounting of chips while increasing velocity of cooling fluid against the chips. Novel techniques of forming a metallization feature across the edge of a chip with high efficiency and manufacturing yield includes enclosure of chips or strips of chips in a tool including a grooved mask or enclosing the chips or strips of chips in a resist which may be exposed and developed using at least a portion of the same tool.

Method of forming a metallization feature on an edge of an IC chip

Method for high density edge mounting of chips

High density edge mounting of chips

Integrated circuit chips (18, 42, or 56) are packaged within openings formed in a substrate such as PCMCIA Card (20, 40, or 54), thus allowing compliance with overall width dimension requirements for standardized electronic components. The arrangement has the advantages that thermal coefficient of expansion of the chips and cards match, and that a sturdy, multilayer ceramic substrate is used for electrical connection to electronic devices such as laptops, palmtops, and the like. In addition, a second integrated circuit chip (68) can be connected directly to the embedded chip (56), thereby allowing two chips to be accommodated in a card (54) at the same location and allowing chip-to-chip electrical communication. A variety of electrical bonding methods joining the embedded chip to the card can be employed. In addition, a variety of thermal conduction arrangements can be used for cooling the embedded integrated circuit chip.

Advanced chip packaging structure for memory card applications

A liquid crystal display is provided wherein a plurality of liquid crystal display tiles are arranged in a matrix and are electrically interconnected to a tile carrier by depositing an electrically conductive metal on a sidewall edge of the liquid crystal display such as by plating, evaporation, or sputtering. Also provided is the method for forming the liquid crystal display.

Liquid crystal display tile interconnected to a tile carrier and method

An integrated circuit package derives increased mechanical robustness and electrical reliability consistent with increased heat dissipation capacity by bonding of integrated circuit chips into a chip stack and bonding the chip stack onto a substrate such as a chip, board, module or another integrated circuit by forming a solder or conductive adhesive bond between a bonding/contact pad on the substrate and a metallization feature extending at least on limited opposing areas of major surfaces of the chip and across the edge of the chip. Thickness of the metallization feature and bonding material provides a 'stand-off' between chips allowing improved heat dissipation by fluid flow, conduction through a viscous thermally conducting material and/or a heat sink disposed between chips in the stack. Novel techniques of forming a metallization feature across the edge of a chip with high efficiency and manufacturing yield includes enclosure of chips or strips of chips in a tool including a grooved mask or enclosing the chips or strips of chips in a resist which may be exposed and developed using at least a portion of the same tool. An application provides a package including heat sinking of a microprocessor master chip in combination with stack of slave chips as memory, logic macros, cross-bar switches and the like which may also include heat sinks between chips in each chip stack.

Chip stacking by edge metallization

A multi-layer printed circuit board or card including at least one passage in at least one of the layers of the circuit board or card for preventing the diffusion of heat throughout the circuit board or card during the securing or removal of components in plated through holes in the circuit board or card by the heating of the plating material to a temperature above a melting point of the plating material.

Method of forming electronic multilayer printed circuit boards or cards

The present invention increases real estate by providing non-annular lands which do not completely encircle the through holes. The non-annular lands are non-annular, that is they do not extend 360.degree. around the through hole. Preferably the non-annular lands contact no more than one side of the through holes thereby providing real estate not otherwise available using conventional lands. The present invention also relates to a method for producing such Non-annular lands.

Non-annular lands

A method of forming a multi-layer circuit board or card. The method includes the step of forming a plurality of conductive planes. The conductive planes include ground, signal, or power planes. At least one through hole is formed through at least one of the conductive planes. An electrically conductive material is deposited onto an inside surface of the at least one through hole to form a plated through hole. At least one thermal relief passage is formed at least in the at least one of the conductive planes for preventing the diffusion of heat throughout the circuit board or card during the securing or removal or chips or other components to the circuit board or card by heating the material deposited in the at least one through hole to a temperature above its melting point. The at least one thermal relief passage is located in the vicinity of the at least one through hole and is free from electrical connection therewith. An electrically insulating material is deposited on at least one side of each of the conductive planes. The planes are placed on top of each other such that a layer of electrically insulating material is located between each of the conductive planes. The conductive planes are joined together to form the multi-layer circuit board or card.

Methods of forming electronic multi-layer printed circuit boards and/or

Multiple circuit functions embodied in electrical circuit lines and areas are supported by a multilayered printed circuit board of various lengths and widths (defining 'x' and 'y' directions) and of various thicknesses (defining a 'z' direction) all on a single board. Several ways of achieving such variations in thickness include providing two layer subassemblies arranged in an alternate and intermediate manner, one subassembly being adapted to support electrical circuit lines and areas, and the other subassembly being formed of thin film dielectric material of various precalculated thicknesses. Another way of achieving a variation in thickness is to limit the surface covered by circuit lines with a pre-calculated core thickness.

Growing community of inventors

Vestal, NY, United States of America

Thurston Bryce Youngs, Jr