Synopsys, Inc.

Cisco Technology, Inc.

Applied Materials, Inc.

Memoir Systems, Inc.

Miradia Inc.

Thu V Nguyen

Jamil Kawa

Sundar Iyer

Shang-Tse Chuang

Sanjeev Joshi

Adam Kablanian

Victor Moroz

Raymond Tak-Hoi Leung

Shih-Yao Christine Sun

Kartik Mohanram

Tzong-Kwang Henry Yeh

Michal Lavi

Raymond Leung

Energy consumption is reduced within an Internet of Things (IoT) device, without degrading operating performance of the corresponding internal circuitry. A first internal supply voltage (VDDa) used to supply the internal circuitry is reduced from a VDD supply voltage to a lower voltage during an idle state, thereby reducing leakage currents in the internal circuitry. The first internal supply voltage (VDDa) may be reduced to a voltage that is one threshold voltage (Vtp) lower than the VDD supply voltage. A second internal supply voltage (VSSa) used to supply the internal circuitry is increased from the VSS supply voltage to a voltage higher than the VSS supply voltage during the idle state, thereby further reducing leakage currents in the internal circuitry. The second internal supply voltage (VSSa) may be increased to a voltage that is one threshold voltage (Vtn) higher than the VSS supply voltage.

Internet of things (IoT) power and performance management technique and circuit methodology

The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for detrapping charges in gate dielectrics in P-channel pull-up transistors and N-channel pull-down transistors in a portion of a static random access memory (SRAM) array due to hot carrier injection (HCI), negative bias temperature instability (NBTI) and positive bias instability (PBTI). This Abstract is not intended to limit the scope of the claims.

Reversing the effects of hot carrier injection and bias threshold instability in SRAMs

A circuit for modeling capacitive coupling comprising a victim line to be tested, a first aggressor line, running alongside the victim line, creating a coupling capacitance between the victim line and the first aggressor line, and a sensor circuit coupled to the victim line, to detect effects of the first aggressor line on the victim line, the sensor circuit measuring timing effects in pseudo-real time.

Measurement of Aggressor/Victim capacitive coupling impact on timing

An automated circuitry that can co-exist in any chip and that allows for a accurate characterization of I*R drops at a block and/or whole chip level is described.

Evaluation of voltage domains in the presence of leakage and/or dynamic switching

A circuit including an SRAM cell with a set of vertical nanowire transistor columns is provided. Each member of the set includes a vertical nanowire transistor and at least one member of the set is a vertical nanowire transistor column including two vertical nanowire transistors in series. The set can consist of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. EDA tools for such circuits are also provided.

Memory cells including vertical nanowire transistors

A circuit is powered through a transistor whose thermal instability behavior is to be evaluated in a stress test. The transistor is stressed during a stress phase of the stress test with a sensor circuit powered off and the Vds of the transistor is zero. The sensor circuit is powered on through the transistor during an evaluate phase of the stress test.

Evaluation of thermal instability stress testing

A circuit skew compensation trigger system comprises a voltage divider including a P-transistor and an N-transistor and a center node in the voltage divider pulled to a first level. The circuit skew compensation trigger system further comprising a trigger to activate when a skew between the P-transistor and the N-transistor is above a threshold. The trigger to initiate a compensator to adjust for the skew.

Circuit skew compensation trigger system

Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the Vpower voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical '0' or logical '1' into either side of the SRAM bit cell.

Methods and apparatus for designing and constructing dual write memory circuits with voltage assist

Multi-port memory circuits are often required within modern digital integrated circuits to store data. Multi-port memory circuits allow multiple memory users to access the same memory cell simultaneously. Multi-port memory circuits are generally custom-designed in order to obtain the best performance or synthesized with logic synthesis tools for quick design. However, these two options for creating multi-port memory give integrated circuit designers a stark choice: invest a large amount of time and money to custom design an efficient multi-port memory system or allow logic synthesis tools to inefficiently create multi-port memory. An intermediate solution is disclosed that allows an efficient multi-port memory array to be created largely using standard circuit cell components and register transfer level hardware design language code.

Methods and apparatus for synthesizing multi-port memory circuits

Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the Vpower voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical '0' or logical '1' into either side of the SRAM bit cell. Thus, spatial domain multiplexing with a voltage assist allows single-ended writes to handle two independent write operations to be handled in a single cycle. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.

Static random access memory (SRAM) circuits are used in most digital integrated circuits to store data. To handle multiple memory users, an efficient dual port six transistor (6T) SRAM memory cell is proposed. The dual port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the SRAM cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two reads in a single cycle using spatial domain multiplexing. Writes can be handled faster that read operations such that two writes can be handled in a single cycle using time division multiplexing. To further improve the operation of the dual port 6T SRAM cell a number of algorithmic techniques are used to improve the operation of the memory system.

Methods and apparatus for designing and constructing multi-port memory circuits

To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the Vpower voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical '0' or logical '1' into either side of the bit cell. Thus, single-ended operation with a voltage assist allows a memory system to handle two concurrent write operations. A write buffer may be added to the memory system to prevent conflicts and thus enable concurrent read operations and write operations in a single cycle.

Methods and apparatus for designing and constructing multi-port memory circuits with voltage assist

A memory cell for driving a complementary pair of electrodes associated with a micro-mirror of a spatial light modulator includes two PMOS transistors coupled to a voltage source providing a source voltage. The two PMOS transistors are characterized by a first size. The memory cell also includes two NMOS transistors coupled to ground. Each of the two NMOS transistors are coupled to one of the two PMOS transistors and are characterized by a second size substantially equal to the first size. The memory cell further includes two word line transistors coupled to a word line and characterized by a third size substantially equal to the first size. Power savings associated with the precharge circuit on the order of (Vdh/Vdl)=36 are achieved in some embodiments.

Low power, small size SRAM architecture

A memory cell for driving a complementary pair of electrodes associated with a micro-mirror of a spatial light modulator. The memory cell includes a first PMOS transistor, wherein a source of the first PMOS transistor is coupled to a first supply voltage. The memory cell also includes a first NMOS transistor, wherein a drain of the first NMOS transistor is coupled to a drain of the first PMOS transistor, a source of the first NMOS transistor is coupled to a second supply voltage, and a gate of the first NMOS transistor is coupled to a gate of the first PMOS transistor. The memory cell further includes a second transistor adapted to establish a conduction path between the gate of the first NMOS transistor and at least one of the first supply voltage or the second supply voltage. Moreover, the memory includes a select transistor, wherein a drain of the select transistor is coupled to the gate of the first NMOS transistor and wherein the memory cell is free from a connection to a fifth transistor.

Growing community of inventors

San Jose, CA, United States of America

Thu V Nguyen