Infineon Technologies Ag

Infineon Technologies Sc300 Gmbh & Co., Kg

Advanced Mask Technology Center Gmbh + Co. Kg

Motorola Corporation

Qimonda Ag

Thorsten Schedel

Sebastian Schmidt

Heiko Hommen

Thomas Fischer

Karl Emerson Mautz

Jens Stäcker

Ralf Otto

Markus Bender

Torsten Seidel

Martin Rössiger

Stefan Ruckmich

Bruno Spuler

Jens Zimmermann

Karl Schumacher

Bernd Zimmermann

Jens Uwe Bruch

Günter Hraschan

Rolf Heine

Andreas Schenke

Volker Berghof

Ines Th&uuml;mmel

Manfred Kraxenberger

Maria De La Piedad Fernandez-Martinez

A photomask mask assembly includes a reflective photomask and a protection structure. The reflective photomask includes a substrate and a reflective multilayer on a first substrate surface of the substrate at a front side of the reflective photomask. The protection structure is on a second substrate surface of the substrate at a backside of the reflective photomask, and is detachable from the reflective photomask at a temperature below 150 degree Celsius.

Photomask assembly with reflective photomask and method of manufacturing a reflective photomask

A reflective photomask includes a substrate with a substrate layer of a low thermal expansion material. The substrate layer includes a main portion of a first structural configuration and an auxiliary portion of a second structural configuration of the low thermal expansion material. The auxiliary portion is formed in a frame section surrounding a pattern section of the substrate. A multilayer mirror is formed on a first surface of the substrate. A reflectivity of the multilayer mirror is at least 50% at an exposure wavelength below 15 nm. A frame trench extending through the multilayer mirror exposes the substrate in the frame section. The auxiliary portion may include scatter centers for out-of-band radiation.

Reflective photomask and reflection-type mask blank

Interconnect structures and methods are disclosed. In one embodiment, an interconnect structure includes a via extendable through a workpiece from a first side of the workpiece to a second side of the workpiece. The via is partially filled with a conductive material and has sidewalls. The interconnect structure includes a contact coupled to the conductive material in the via proximate the first side of the workpiece. The conductive material in the via comprises a recessed region comprising a landing zone proximate the second side of the workpiece.

Interconnect structures and methods

By a unit for determining fractions of a substance in a gas or gas mixture, measurements are carried out on the gas or gas mixture for purging a lens in a projection apparatus for projecting patterns onto a substrate. The results of a first measurement on the gas fed to the lens are compared with the results of a measurement of the gas removed from the lens. If, the substance is a contaminating substance that leads to a deposit on the lens under the influence of high-energy radiation from an illumination source, the difference is used to infer photochemical reactions on the surface of the lens that lead disadvantageously to the deposition. A signal is generated as a consequence of the comparison and is used to take preventive measures against a degradation of the lens. Mass spectrometers, electric or optical sensors and other known methods for substance analysis are used as measurement units.

Method for purging an optical lens

The unevennesses of a chuck are measured at various positions and are stored, as discrepancies from an idealized plane, in a databank. The measured discrepancies are used to calculate corrections for the predetermined settings for the focus distance and/or the tilt of the chuck. These corrections are in each case used differently for adjusting the respective exposure of the exposure areas.

Method for adjusting a substrate in an appliance for carrying out exposure

A measurement mark () for determining the relative positional accuracy of a progressive projection onto a wafer (), the projection being performed with two masks (), comprising two structure elements () formed on a respective one of the masks (). The structure elements () overlap with regard to their position on the masks so that, during the projection of the second structure element (), an electrically conductive structure () formed on the basis of the first structure element on the wafer () is overformed by removal of a portion (). In an electrical line width measurement, the reduced width (CD, CD) of the structure () is measured and compared either with the original width () or with that width (CD) of a further partial element () produced by the overforming.

Method for determining the relative positional accuracy of two structure elements on a wafer

A batch of semiconductor wafers are exposed after an alignment in a wafer stepper or scanner and each of their alignment parameters are determined. Using, e.g., a linear formula with tool specific coefficients, the overlay accuracy can be calculated from these alignment parameters in advance with a high degree of accuracy as if a measurement with an overlay inspection tool had been performed. The exposure tool-offset can be adjusted on a wafer-to-wafer basis to correct for the derived overlay inaccuracy. Moreover, the alignment parameters for a specific wafer can be used to change the tool-offset for the same wafer prior to exposure. The required inspection tool capacity is advantageously reduced, the wafer rework decreases, and time is saved to perform the exposure step.

Method for exposing at least one or at least two semiconductor wafers

In an alignment or overlay measurement of patterns on a semiconductor wafer an error that occurs during the measurement in one of a predefined number of alignment structures in an exposure field of a corresponding predefined set of exposure fields can be handled by selecting an alignment structure in a substitute exposure field. The latter exposure field need not be part of the predefined set of exposure fields, that is, an inter-field change may be effected. The number of alignment measurements on a wafer remains constant and the quality is increased. Alternatively, when using another alignment structure in the same exposure field&#x2014;by effecting an intra-field change&#x2014;the method becomes particularly advantageous when different minimum structure sizes are considered for the substitute targets. Due to the different selectivity in, say, a previous CMP process, such targets might not erode and do not cause an error in a measurement, thus providing an increased alignment or overlay quality.

Method for performing an alignment measurement of two patterns in different layers on a semiconductor wafer

Processing parameters of at least one plate-shaped object, e.g. a semiconductor device or wafer, or a flat panel display, in a processing tool are adjusted depending on which processing device out of at least one set of processing devices has been used for the semiconductor device in a preceding step. A virtual or physical tag is generated, which connects the semiconductor device identification with the processing device identification. This enables a compensation of tool-dependent effects in previous processing of a single device. An example is chemical mechanical polishing prior to lithography, where alignment marks can be deteriorated differently between CMP-units. The amount of compensation is detected and evaluated by metrology tools, which&#x2014;depending on the sequence of the metrology step relative to the processing step to be adjusted&#x2014;either feed-forward or feed-backward their results to the processing tool. The yield of semiconductor device production is advantageously increased.

Method for adjusting processing parameters of at least one plate-shaped object in a processing tool

A method for exposing a semiconductor wafer compensates for the effects of process inhomogeneities, e.g. in semiconductor etching or deposition processes, by individually adjusting sets of exposure parameters of an exposure tool for any exposure field. The exposure parameters are preferably the dose and the focus, which are varied across the semiconductor wafer.

Method for exposing a semiconductor wafer

Exposure positions of exposure fields of semiconductor wafers are subsequently corrected individually in order to compensate for processes affecting the locational position of alignment marks and/or oblique measurement structures. Measurement structures are formed preferably in the frame region of product wafers comprising electrical circuits to be formed and their locational positions before and after the effect of the process that has an effect are compared individually for purpose of determining the positional displacement for each relevant exposure field. From this there is determined either directly a 'shot'-fine correction value for the individual exposure or at least one nonlinear function for the correction in dependence on the position of the measurement structures on the wafer. The corrections are applied to the exposure fields after alignment to the alignment marks overformed by the process in dependence on their position on the wafer.

Method for aligning and exposing a semiconductor wafer

A test reticle having a pad and antenna structures with varying critical dimensions is provided to measure sidewall angles developing in the resist sidewalls of clear lines. These sidewall angles originate from resist flow due to the occurrence of excessively high temperatures in a resist process on a lithographic track after the exposure of a semiconductor wafer. A scanning electron microscope is used to perform the measurement. A sequence of temperatures is applied in each postbake step to process a wafer, and the sidewall angle is determined afterwards from e.g. a critical dimension measurement with a known resist thickness. An error signal is issued, if a threshold value of a sidewall angle is exceeded. The temperature of the resist process, e.g. the postbake, is then adjusted to a temperature below the temperature causing the warning signal.

Method for adjusting a temperature in a resist process

After exposing a semiconductor wafer, quality parameters, for example, the critical dimension, the overlay accuracy, and alignment parameters, etc. are measured in successive inspections and are compared with tolerance range widths that are specified dynamically by calculating the range from measured values of one or more of the other quality parameters. For example, the tolerance range width for the overlay accuracy can be increased for smaller measured critical dimension values of the same structures without affecting the functionality of the integrated circuit. Using a forward mechanism, the tolerance ranges can also be adjusted with the quality parameter measurements from a first layer to the quality parameter tolerance range width of a second layer.

Method for controlling the quality of a lithographic structuring step

While a first leading semiconductor wafer ( ) already processed in a process appliance ( ) and belonging to a batch is being measured in a microscope measuring instrument ( ) in relation to values for the structure parameters a second or further semiconductor wafer ( ) belonging to the batch is processed in the process appliance ( ). An event signal ( ) reports, for example, an inspection carried out successfully of the first wafer, so that the following wafers ( ) no longer need to be inspected. Using the measured results, the process parameters ( ) of the process appliance ( ) are automatically readjusted. Events such as maintenance work or parameter drifts in trend maps etc. are detected in control units ( or ) and, via the output of an event signal ( ), for example in an event database ( ), lead to the event-based selection of structure parameters ( ) to be measured and/or to the initiation of a leading wafer ( ). Limiting-value violations ( ) of at least one process parameter ( ), detected by a control unit ( ), are responded to by a warning signal ( ) and likewise fed into the event database ( ).

Method for controlling a processing device for a sequential processing of semiconductor wafers

There is disclosed a method for clamping a semiconductor wafer, preferably suitable for a wafer with a diameter of 300 mm or larger. After depositing at least one encapsulating material layer over the front side and backside of the wafer, the material layer over the front side of the wafer is etched selectively to form a predetermined structure in following process steps. Wafer warpage is caused as a result of unequal wafer bowing stress of the material layer. By removing the material layer over the backside of the wafer partially or completely in accordance with the desired reduction of the bowing stress wafer warpage is reduced. In a further course of the manufacturing process, the semiconductor device is clamped electrostatically, physically or by use of vacuum.

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Dresden, Germany

Thorsten Schedel