Advanced Micro Devices Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Globalfoundries Dresden Module One Limited Liability Company & Co. Kg.

Thorsten E Kammler

Andy C Wei

Manfred Horstmann

Jan Hoentschel

Karsten Wieczorek

Paul Raymond Besser

Stephan Kronholz

Peter Javorka

Markus Lenski

Roman Boschke

Scott Luning

Carsten Reichel

Peter Baars

Errol Todd Ryan

Simon Siu-Sing Chan

Christoph Schwan

Christof Streck

Robert J Chiu

Jeffrey P Patton

Austin Frenkel

Annekathrin Zeun

Ralf Richter

Scott D Luning

Eric N Paton

William George En

Rolf Stephan

Andreas Knorr

Maciej Wiatr

Akif Sultan

Thomas Feudel

Ralf Van Bentum

Igor V Peidous

Gunter Grasshoff

Andreas Gehring

Casey Scott

Michael Raab

Katja Huy

Joe Bloomquist

Indradeep Sen

Andreas Hellmich

Ina Ostermay

Minh Van Ngo

Sven Beyer

Thilo Scheiper

Darin A Chan

Matthias Schaller

Hans-Peter Moll

Paul L King

Elliot John Smith

Frank Wirbeleit

Martin Trentzsch

Juergen Faul

Martin Gerhardt

Linda R Black

Nan Wu

Heike Salz

Carsten Grass

Jürgen Faul

Gunda Beernink

Volker Grimm

Wolfgang Buchholtz

Karla Romero

Robert Mulfinger

Hans Van Meer

Joerg Radecker

Steffen A Sichler

Fernando Koch

Guido Koerner

Sylvain Henri Baudot

Jochen Rinderknecht

Inka Zienert

Scott Lunning

The present disclosure relates to semiconductor devices, and more particularly, to high voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG) and methods of manufacture. A structure of the present disclosure includes a plurality of extended drain MOSFET (EDMOS) devices on a high voltage well with a split-gate dielectric material including a first gate dielectric material and a second gate dielectric material, the second gate dielectric material including a thinner thickness than the first gate dielectric material, and a high-k dielectric material on the split-gate dielectric material.

High voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG)

The present disclosure relates to semiconductor structures and, more particularly, to co-integrated high voltage and medium voltage devices and methods of manufacture. The structure includes a substrate having a semiconductor on insulator (SOI) region and a bulk region; and a first device formed on the bulk region, the first device having a first gate dielectric layer and a second gate dielectric layer surrounding the first dielectric layer, and a thickness of the first gate dielectric layer and the second gate dielectric layer being greater than a thickness of an insulator layer of the SOI region.

Co-integrated high voltage (HV) and medium voltage (MV) field effect transistors

In fully depleted SOI transistors, specifically designed semiconductor materials may be provided for different types of transistors, thereby, for instance, enabling a reduction of hot carrier injection in transistors that are required to be operated at a moderately high operating voltage. To this end, well-controllable epitaxial growth techniques may be applied selectively for one type of transistor, while not unduly affecting the adjustment of material characteristics of a different type of transistor.

Process for forming semiconductor layers of different thickness in FDSOI technologies

A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.

Method of forming a semiconductor device structure using differing spacer widths and the resulting semiconductor device structure

A method of forming a gate structure over a hybrid substrate structure with topography having a bulk region and an SOI region is disclosed including forming a gate material layer above the SOI and bulk regions, forming a mask layer above the gate material layer, forming a first planarization layer above the mask layer, forming a first gate structure masking pattern above the first planarization layer, patterning the first planarization layer in alignment with the first gate structure masking pattern, and patterning the mask layer in accordance with the patterned first planarization layer, resulting in a gate mask disposed above the gate material layer.

Method of forming a gate mask for fabricating a structure of gate lines

A semiconductor structure includes a substrate, at least one electrically conductive pillar provided over the substrate and an electrically conductive structure provided over the substrate. The electrically conductive pillar includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure also includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure annularly encloses each of the at least one electrically conductive pillar. The outer layer of each of the at least one electrically conductive pillar contacts the outer layer of the electrically conductive structure. The outer layer of the at least one electrically conductive pillar and the outer layer of the electrically conductive structure are formed of different metallic materials.

Semiconductor structure including at least one electrically conductive pillar, semiconductor structure including a contact contacting an outer layer of an electrically conductive structure and method for the formation thereof

By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.

SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto

A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.

Shallow pn junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process

A semiconductor device is formed with low resistivity self aligned silicide contacts with high-K/metal gates. Embodiments include postponing silicidation of a metal layer on source/drain regions in a silicon substrate until deposition of a high-K dielectric, thereby preserving the physical and morphological properties of the silicide film and improving device performance. An embodiment includes forming a replaceable gate electrode on a silicon-containing substrate, forming source/drain regions, forming a metal layer on the source/drain regions, forming an ILD over the metal layer on the substrate, removing the replaceable gate electrode, thereby forming a cavity, depositing a high-K dielectric layer in the cavity at a temperature sufficient to initiate a silicidation reaction between the metal layer and underlying silicon, and forming a metal gate electrode on the high-K dielectric layer.

Self-aligned silicidation for replacement gate process

Generally, the subject matter disclosed herein is directed to semiconductor devices with reduced threshold variability having a threshold adjusting semiconductor material in the device active region. One illustrative semiconductor device disclosed herein includes an active region in a semiconductor layer of a semiconductor device substrate, the active region having a region length and a region width that are laterally delineated by an isolation structure. The semiconductor device further includes a threshold adjusting semiconductor alloy material layer that is positioned on the active region substantially without overlapping the isolation structure, the threshold adjusting semiconductor alloy material layer having a layer length that is less than the region length. Additionally, the disclosed semiconductor device includes a gate electrode structure that is positioned above the threshold adjusting semiconductor alloy material layer, the gate electrode structure including a high-k dielectric material and a metal-containing electrode material formed above the high-k dielectric material.

Semiconductor device with reduced threshold variability having a threshold adjusting semiconductor alloy in the device active region

By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss

Methods and provided for fabricating a semiconductor IC having a hardened shallow trench isolation (STI). In accordance with one embodiment the method includes providing a semiconductor substrate and forming an etch mask having an opening exposing a portion the semiconductor substrate. The exposed portion is etched to form a trench extending into the semiconductor substrate and an oxide is deposited to at least partially fill the trench. At least the surface portion of the oxide is plasma nitrided to form a nitrided oxide layer and then the etch mask is removed.

Methods of fabricating a semiconductor IC having a hardened shallow trench isolation (STI)

The threshold voltage of a sophisticated transistor may be adjusted by providing a specifically designed semiconductor alloy in the channel region of the transistor, wherein a negative effect of this semiconductor material with respect to inducing a strain component in the channel region may be reduced or over-compensated for by additionally incorporating a strain-adjusting species. For example, a carbon species may be incorporated in the channel region, the threshold voltage of which may be adjusted on the basis of a silicon/germanium alloy of a P-channel transistor. Consequently, sophisticated metal gate electrodes may be formed in an early manufacturing stage.

Adjusting of strain caused in a transistor channel by semiconductor material provided for threshold adjustment

In a static memory cell, the failure rate upon forming contact elements connecting an active region with a gate electrode structure formed above an isolation region may be significantly reduced by incorporating an implantation species at a tip portion of the active region through a sidewall of the isolation trench prior to filling the same with an insulating material. The implantation species may represent a P-type dopant species and/or an inert species for significantly modifying the material characteristics at the tip portion of the active region.

Leakage control in field effect transistors based on an implantation species introduced locally at the STI edge

A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.

Method of forming a field effect transistor

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Dresden, Germany

Thorsten E Kammler