Lam Research Corporation

Applied Materials, Inc.

Other

Centre National De La Recherche Scientifique

The United States of America As Represented by the United States

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Lam Research Ag

Thorsten B Lill

Meihua Shen

Harmeet Singh

Ivan L Berry, Iii

Jeffrey S Marks

Wenbing Yang

Andreas Fischer

Samantha SiamHwa Tan

Keren Jacobs Kanarik

Taeseung Kim

John Hoang

Richard Janek

Alex Paterson

Michael N Grimbergen

Vahid Vahedi

Gowri Kamarthy

Yang Pan

Mariusch Gregor

Dennis Michael Hausmann

Matthew Fenton Davis

Sirish K Reddy

Andrew D Bailey, Iii

Jeffrey D Chinn

Baosuo Zhou

Padmapani Nallan

Thomas W Mountsier

Joydeep Guha

Aaron Eppler

Kaushik Chattopadhyay

Srinivas D Nemani

Jennifer Y Sun

Ellie Y Yieh

John Patrick Holland

Richard Stephan Wise

Nicolas Posseme

Ren-Guan Duan

Hui-Jung Wu

Lei Lian

Olivier Joubert

Anthony J Ricci

James Samuel Sims

Nerissa Sue Draeger

Shashank C Deshmukh

Benjamin Schwarz

Samantha S H Tan

Jorge Luque

Luc Albarede

David Trussell

Valentin N Todorov

Andrew John McKerrow

Monica Titus

Yassine Kabouzi

Kathryn Merced Kelchner

Alexander Dulkin

Shane Tang

Jeff Chinn

Mohit Kumar Jain

Kartik Ramaswamy

Kenneth S Collins

Dmitry Lubomirsky

Paul Raymond Besser

Wei Liu

Bart Jan Van Schravendijk

Christopher Dennis Bencher

Klaus Florian Schuegraf

Shahid Rauf

Shaoher X Pan

Alan M Schoepp

Richard Alan Gottscho

David Charles Smith

Richard Howard Gould

Nicolas J Bright

Ankur Agarwal

Hyungsuk Alexander Yoon

Michael J Pellin

David J Hemker

Saravanapriyan Sriraman

Anisul Haque Khan

Nagraj Shankar

David S Mui

Dragan Valentin Podlesnik

Harald F Okorn-Schmidt

Alan Hiroshi Ouye

Mark Naoshi Kawaguchi

Diane J Hymes

Gary Bultman

Weimin Zeng

Ji Zhu

Jisoo Kim

Uday Mitra

Ananda K Banerji

David S L Mui

Nicolas Gani

Jinhan Choi

Yifeng Zhou

Philipp Engesser

Kevin M McLaughlin

Songlin Xu

Stephen Yuen

Laurent J Vallier

Patterned magnetoresistive random access memory (MRAM) stacks are formed by performing a main etch through a plurality of MRAM layers disposed on a substrate, where the main etch includes using ion beam etching (IBE). After the main etch, gapfill dielectric material is deposited in spaces between the patterned MRAM stacks, and the gapfill dielectric material is selectively etched or otherwise formed to an etch depth that is above a depth of an underlayer. After the gapfill dielectric material is formed, at least some of the gapfill dielectric material and any electrically conductive materials deposited on sidewalls of the patterned MRAM stacks are removed by performing an IBE trim etch.

Ion beam etching with sidewall cleaning

Apparatuses and methods are provided. Some methods may include providing a substrate to a processing chamber, the substrate having a first material adjacent to and covering a surface of a second material, modifying a layer of the first material by flowing a first process gas onto the substrate and thereby creating a modified layer of the first material, removing the modified layer of the first material by flowing a second process gas onto the substrate, and converting, when the surface of the second material is uncovered via removal of the modified layer, the surface to a converted layer of the second material by flowing a third process gas onto the substrate, in which the first and second process gases are less reactive with the converted layer than with the first material and the second material.

Etch selectivity control in atomic layer etching

Non-elastomeric, non-polymeric, non-metallic membrane valves for use in high-vacuum applications are disclosed. Such valves are functional even when the fluid-control side of the valve is exposed to a sub-atmospheric pressure field which may generally act to collapse/seal traditional elastomeric membrane valves.

Non-elastomeric, non-polymeric, non-metallic membrane valves for semiconductor processing equipment

A method for fabricating a plurality of resistive random access memory (RRAM) cells includes providing a substrate including a memory medium arranged on an underlying layer; creating channel holes in the memory medium having a first critical dimension in a range from 1 nm to 20 nm; depositing switching material defining a filament of the RRAM cells in the channel holes; depositing a top electrode of the RRAM cells on the memory medium and the switching material; and separating adjacent ones of the RRAM cells by etching the top electrode and the memory medium between adjacent ones of the channel holes.

Resistive random access memory with preformed filaments

A processing chamber and method of etching a semi-conductor substrate are presented. The processing chamber is symmetric, with the centerlines of a chuck and stem of a stage to retain a semi-conductor substrate aligned with a centerline of a passage in a core of a pump used to evacuate the processing chamber and with a center-line of a gas port through which gas is introduced to the processing chamber. The stem extends through the passage and a spiral groove is formed in the passage in only one of the stem or an inner surface of the core to provide pumping action to counter back streaming of the gas from an exhaust of the pump in an intermediate and viscous flow regime inside a gap between the stem and the core.

Turbomolecular pump and cathode assembly for etching reactor

Methods for forming patterned multi-layer stacks including a metal-containing layer are provided herein. Methods involve using silicon-containing non-metal materials in a multi-layer stack including one sacrificial layer to be later removed and replaced with metal while maintaining etch contrast to pattern the multi-layer stack and selectively remove the sacrificial layer prior to depositing metal. Methods involve using silicon oxycarbide in lieu of silicon nitride, and a sacrificial non-metal material in lieu of a metal-containing layer, to fabricate the multi-layer stack, pattern the multi-layer stack, selectively remove the sacrificial non-metal material to leave spaces in the stack, and deposit metal-containing material into the spaces. Sacrificial non-metal materials include silicon nitride and doped polysilicon, such as boron-doped silicon.

Film stack simplification for high aspect ratio patterning and vertical scaling

Methods and apparatuses for forming an encapsulation bilayer over a chalcogenide material on a semiconductor substrate are provided. Methods involve forming a bilayer including a barrier layer directly on chalcogenide material deposited using pulsed plasma plasma-enhanced chemical vapor deposition (PP-PECVD) and an encapsulation layer over the barrier layer deposited using plasma-enhanced atomic layer deposition (PEALD). In various embodiments, the barrier layer is formed using a halogen-free silicon precursor and the encapsulation layer deposited by PEALD is formed using a halogen-containing silicon precursor and a hydrogen-free nitrogen-containing reactant.

Conformal damage-free encapsulation of chalcogenide materials

An apparatus may be provided that includes a substrate having one or more microfluidic valve structures. The valve structures are non-elastomeric, non-polymeric, non-metallic membrane valves for use in high-vacuum application. Such valves are functional even when the fluid-control side of the valve is exposed to a sub-atmospheric pressure field which may generally act to collapse/seal traditional elastomeric membrane valve.

A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.

Self-aligned vertical integration of three-terminal memory devices

Disclosed are apparatuses and methods for performing atomic layer etching. A method may include modifying one or more surface layers of material on the substrate and exposing the one or more modified surface layers on the substrate to an electron source thereby removing, without using a plasma, the one or more modified surface layers on the substrate. An apparatus may include a processing chamber, a process gas unit, an electron source, and a controller with instructions configured to cause the process gas unit to flow a first process gas to a substrate in a chamber interior, the first process gas is configured to modify one or more layers of material on the substrate, and to cause the electron source to generate electrons and expose the one or more modified surface layers on the substrate to the electrons, the one or more modified surface layers being removed, without using a plasma.

Electron excitation atomic layer etch

Etch in a thermal etch reaction is predicted using a machine learning model. Chemical characteristics of an etch process and associated energies in one or more reaction pathways of a given thermal etch reaction are identified using a quantum mechanical simulation. Labels indicative of etch characteristics may be associated with the chemical characteristics and associated energies of the given thermal etch reaction. The machine learning model can be trained using chemical characteristics and associated energies as independent variables and labels as dependent variables across many different etch reactions of different types. When chemical characteristics and associated energies for a new thermal etch reaction are provided as inputs in the machine learning model, the machine learning model can accurately predict etch characteristics of the new thermal etch reaction as outputs.

Predicting etch characteristics in thermal etching and atomic layer etching

Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate.

Thermal atomic layer etch with rapid temperature cycling

The embodiments herein relate to methods and apparatus for etching features in semiconductor substrates. In a number of cases, the features may be etched while forming a spin-torque-transfer random access memory (STT-RAM) device. In various embodiments, the substrate may be cooled to a low temperature via a cooled substrate support during particular processing steps. The cooled substrate support may have beneficial impacts in terms of reducing the degree of diffusion-related damage in a resulting device. Further, the use of a non-cooled substrate support during certain other processing steps can likewise have beneficial impacts in terms of reducing diffusion-related damage, depending on the particular step. In some implementations, the cooled substrate support may be used in a process to preferentially deposit a material (in some cases a reactant) on certain portions of the substrate.

Ion beam etching utilizing cryogenic wafer temperatures

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Sunnyvale, CA, United States of America

Thorsten B Lill