Globalfoundries Inc.

Advanced Micro Devices Corporation

Thomas Werner

Frank Feustel

Kai Frohberg

Michael Grillberger

Joerg Hohage

Oliver Aubel

Ralf Richter

Uwe Griebenow

Hartmut Ruelke

Robert Seidel

Peter Baars

Carsten Peters

Andy C Wei

Thilo Scheiper

Matthias Lehr

Matthias Schaller

Jens Heinrich

Juergen Boemmels

John G Pellerin

Gunter Grasshoff

Frank Koschinsky

Holger S Schuehrer

Massud Aminpur

Carsten Hartig

Patrick Press

Frank Seliger

Frank Richter

Bernd Schulz

Johannes F Groschopf

Frank Mauersberger

Vivien Schroeder

Massud Abubaker Aminpur

Georg Talut

Mathias Böttcher

Michael Kiene

Peter Hübler

Frank Feustal

Ruo Qing Su

In a method of forming a three-dimensional semiconductor device, a first chip is provided that includes a first substrate, a first device layer positioned on and covering the first substrate, and a first metallization system positioned on and covering the first device layer, wherein the first device layer includes a plurality of first transistor elements. A second chip is also provided and includes a second substrate, a second device layer positioned on and covering the second substrate, and a second metallization system positioned on and covering the second device layer, wherein the second device layer includes a plurality of second transistor elements. The second chip is attached to the first chip so that a heat spreading material is positioned between the first chip and the second chip and covers at least a portion of the first metallization system.

Methods of forming 3-D integrated semiconductor devices having intermediate heat spreading capabilities

A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.

Wafer with improved plating current distribution

A semiconductor structure includes a semiconductor substrate, one or more interconnect layers provided over the substrate and a circuit. The circuit includes a plurality of circuit elements formed at the substrate and a plurality of electrical connections provided in the one or more interconnect layers. A die seal is provided in the one or more interconnect layers. A die seal leakage detection material is arranged in the one or more interconnect layers between the die seal and the plurality of electrical connections. The die seal provides a protection of the die seal leakage detection material from moisture if the die seal is intact. The die seal leakage detection material is adapted for providing a detectable modification of the circuit after an exposure of the die seal leakage detection material to moisture.

Semiconductor structure including a die seal leakage detection material, method for the formation thereof and method including a test of a semiconductor structure

The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at least a first connecting line arranged in a first vertical level and a second connecting line arranged in a second vertical level, different from the first vertical level, and a breakdown prevention layer placed in at least part of the vertical space separating the first connecting line from the second connecting line.

Vertical breakdown protection layer

In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips.

3-D integrated semiconductor device comprising intermediate heat spreading capabilities

In a metallization system of a complex semiconductor device, metal pillars, such as copper pillars, may be formed in a nail-like configuration in order to reduce the maximum mechanical stress acting on the metallization system while providing a required contact surface for connecting to the package substrate. The nail-like configuration may be obtained on the basis of appropriately configured resist masks.

Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom

In a metallization system of a semiconductor device, a transition via may be provided with an increased degree of tapering by modifying a corresponding etch sequence. For example, the resist mask for forming the via opening may be eroded once or several times in order to increase the lateral size of the corresponding mask opening. Due to the pronounced degree of tapering, enhanced deposition conditions may be accomplished during the subsequent electrochemical deposition process for commonly filling the via opening and a wide trench connected thereto.

Metallization system of a semiconductor device comprising extra-tapered transition vias

In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element.

Restricted stress regions formed in the contact level of a semiconductor device

The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.

Method for increasing penetration depth of drain and source implantation species for a given gate height

Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material.

Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions

Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors.

Self-aligned multiple gate transistor formed on a bulk substrate

In sophisticated semiconductor devices, the integrity of the device level may be enhanced after applying a replacement gate approach by providing an additional diffusion barrier layer, such as a silicon nitride layer, thereby obtaining a similar degree of diffusion blocking capabilities as in semiconductor devices without performing a replacement gate approach.

Method for making semiconductor device comprising replacement gate electrode structures with an enhanced diffusion barrier

A semiconductor chip and a package substrate may be directly connected on the basis of form closure by providing appropriately shaped complementary contact structures in the semiconductor chip and the package substrate. Consequently, solder material may no longer be required and thus any elevated temperatures during the assembly process may be avoided, which may conventionally result in significant stress forces, thereby creating damage, in particular in very complex metallization systems.

Stress reduction in chip packaging by using a low-temperature chip-package connection regime

In sophisticated metallization systems, vertical contacts and metal lines may be formed on the basis of a dual inlaid strategy, wherein an edge rounding or corner rounding may be applied to the trench hard mask prior to forming the via openings on the basis of a self-aligned via trench concept. Consequently, self-aligned interconnect structures may be obtained, while at the same time providing superior fill conditions during the deposition of barrier materials and conductive fill materials.

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Moritzburg, Germany

Thomas Werner