Novellus Systems Incorporated

Lam Research Corporation

Other

International Business Machines Corporation

Thomas W Mountsier

Bart Jan Van Schravendijk

Steven T Mayer

Thorsten B Lill

Harmeet Singh

Roey Shaviv

Vahid Vahedi

Nagraj Shankar

Sirish K Reddy

Yongsik Yu

Joydeep Guha

Aaron Eppler

Kaushik Chattopadhyay

William Crew

Michael Carris

Karen Billington

Atul Gupta

Ming Chu Li

Dennis Michael Hausmann

Shankar Swaminathan

Michael Jay Shapiro

Mandyam Sriram

Ramesh Chandrasekharan

Jon Henri

Hu Kang

Easwar Srinivasan

Jeffrey A Tobin

Nader Shamma

Ananda K Banerji

Mahesh K Sanganeria

Antonio Xavier

Glenn B Alers

Timothy Patrick Cleary

Thomas G Jewell

Daniel A Koos

Heung L Park

Tom Dorsh

Bryan Schlief

Robert T Rozbicki

Adrien Lavoie

S M Reza Sadjadi

Bhadri N Varadarajan

Patrick A Van Cleemput

Hui-Jung Wu

Ronald Allan Powell

Jianou Shi

Adrien LaVoie

William T Lee

Vinay Pohray

James C Wing

Bart K Van Schravendijk

Chiu Chi

Si Yi Li

Jean Qing Lu

Wen Wu

Mary Anne Plano

Hong Mei Zhang

Stephan Lassig

Michael D Kilgore

Joseph R Laia, Jr

Christopher J Rau

Donald Schlosser

Don Schlosser

James C Oswalt

Wilbert G M Van Den Hoek

A method for etching features in an OMOM stack with first layer of silicon oxide, a second layer of a metal containing material over the first layer, a third layer of silicon oxide over the second layer, and a fourth layer of a metal containing material over the third layer is provided. A hardmask is formed over the stack. The hardmask is patterned. The OMOM stack is etched through the hardmask.

High aspect ratio etch of oxide metal oxide metal stack

A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.

High aspect ratio etch with combination mask

Provided herein are multi-layer stacks for use in extreme ultraviolet lithography tailored to achieve optimum etch contrast to shrink features and smooth the edges of features while enabling use of an optical leveling sensor with little or reduced error. The multi-layer stacks may include an atomically smooth layer with an average local roughness of less than a monolayer, and one or more underlayers, which may be between a target layer to be patterned and a photoresist. Also provided are methods of depositing multi-layer stacks for use in extreme ultraviolet lithography.

PECVD films for EUV lithography

A dielectric diffusion barrier is deposited on a substrate that has a via and an overlying trench etched into an exposed layer of inter-layer dielectric, wherein there is exposed metal from the underlying interconnect at the bottom of the via. In order to provide a conductive path from the underlying metallization layer to the metallization layer that is being formed over it, the dielectric diffusion barrier is formed selectively on the inter-layer dielectric and not on the exposed metal at the bottom of the via. In one example a dielectric SiNC diffusion barrier layer is selectively deposited on the inter-layer dielectric using a remote plasma deposition and a precursor that contains both silicon and nitrogen atoms. Generally, a variety of dielectric diffusion barrier materials with dielectric constants of between about 3.0-20.0 can be selectively formed on inter-layer dielectric.

Selective formation of dielectric barriers for metal interconnects in semiconductor devices

Various embodiments herein relate to formation of contact etch stop layers in the context of forming gates and contacts. In certain embodiments, a novel process flow is used, which may involve the deposition and removal of a sacrificial pre-metal dielectric material before a particular contact etch stop layer is formed. An auxiliary contact etch stop layer may be used in addition to a primary etch stop layer that is deposited previously. In certain cases the contact etch stop layer is a metal-containing material such as a nitride or an oxide. The contact etch stop layer may be deposited through a cyclic vapor deposition in some embodiments. The process flows disclosed herein provide improved protection against over-etching gate stacks, thereby minimizing gate-to-contact leakage. Further, the disclosed process flows result in wider flexibility in terms of materials and deposition conditions used for forming various dielectric materials, thereby minimizing parasitic capacitance.

Sacrificial pre-metal dielectric for self-aligned contact scheme

Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.

Plasma activated conformal film deposition

Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.

Multistep method of depositing metal seed layers

Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier layer may contain copper. In some embodiments, the layers have conductivity sufficient for direct electroplating of conductive materials without needing intermediate seed layers. Such barrier layers may be used with circuits lines that are less than 65 nm wide and, in certain embodiments, less than 40 nm wide. The barrier layer may be passivated to form easily removable layers including sulfides, selenides, and/or tellurides of the materials in the layer.

Diffusion barrier layers

Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.

Protection of Cu damascene interconnects by formation of a self-aligned buffer layer

The present invention provides a low dielectric constant copper diffusion barrier film composed, at least in part, of boron-doped silicon carbide suitable for use in a semiconductor device and methods for fabricating such a film. The copper diffusion barrier maintains a stable dielectric constant of less than 4.5 in the presence of atmospheric moisture.

Low-k b-doped SiC copper diffusion barrier films

An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting. After the metal regions are etched and recessed in the substrate surface, a conductive capping layer is formed using electroless deposition over the recessed exposed metal regions.

Fabrication of semiconductor interconnect structure

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San Jose, CA, United States of America

Thomas W Mountsier