Agere Systems Inc.

Thomas Michael Wolf

Allen Yen

John Martin McIntosh

Steven Alan Lytle

Stephen Arlon Meisner

Stephen Ward Downey

Paul B Murphey

Cynthia C Lee

Alberto Santoni

The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.

Define via in dual damascene process

A method for nondestructively characterizing alignment overlay between two layers of a semiconductor wafer. An incident beam of radiation is directed upon the wafer surface and the properties of the resulting diffracted beam are determined, in one embodiment as a function of wavelength or incident angle. The spectrally or angularly resolved characteristics of the diffracted beam are related to the alignment of the overlay features. A library of calculated diffraction spectra is established by modeling a full range of expected variations in overlay alignment. The spectra resulting from the inspection of an actual wafer having alignment targets in at least two layers is compared against the library to identify a best fit to characterize the actual alignment. The results of the comparison may be used as an input for upstream and/or downstream process control.

Overlay metrology using scatterometry profiling

A process ( ) for forming a metal interconnect ( ) in a semiconductor device ( ) using a photoresist layer ( ) having a thickness (T) of no more than 0.66 microns without forming a notch in the side ( ) of the interconnect. A reactive ion etching process ( ) used to remove portions of a metal layer ( ) to form the interconnect includes a burst etch step ( ) wherein a first high flow rate ( ) of passivation gas is delivered, followed by a main metal etch step ( ) wherein the flow rate of passivation gas is reduced to a second lower value.

Method for avoiding notching in a semiconductor interconnect during a metal etching step

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Orlando, FL, United States of America

Thomas Michael Wolf