International Business Machines Corporation

Bae Systems Information and Electronic Systems Integration Inc.

Thomas M Storey

Johnny James LeBlanc

Joseph W Yoder

Edward J Spall

Ronald C Todd

Michael J Bear

Bruce McWilliam

Henry C Baron

A procedure for temporally isolating an environmentally dependent integrated circuit fault includes the steps of determining a marginally failing and a minimally passing environmental condition corresponding to the fault; identifying a clock cycle Tat which the fault was first detected; determining a candidate clock cycle at which the fault may have occurred; and iteratively a) applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; b) applying remaining test patterns under the minimally passing environmental condition; and c) adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application up through the candidate clock cycle under the marginally failing environmental condition. Candidate clock cycle adjustment in accordance with a binary search technique enables determination of an exact clock cycle at which the fault occurred in a maximum of Log(T+1) iterations.

System and method for temporally isolating environmentally sensitive integrated circuit faults

Multi-pattern data retention testing and iterative change of measurement testing are used for the production of Known Good Dies. Multi-pattern data testing of a memory such as an SRAM comprises writing at V , reduction of V , restoration of V , reading of the memory, and comparison of write patterns to read patterns to determine accuracy of data retention. Iterative or change of measurement testing involves repeated testing of a die to determine changes in Iddq, changes in multi-pattern data retention, or other changes in chip operating parameters. Defect activating test may be used in combination with change of measurement testing or with multi-pattern data retention testing.

Method for testing of known good die

A multichip module (MCM) and associated fabrication technique are presented wherein a test circuit is disposed within the interposer substrate of the MCM to facilitate testing of the module's integrated circuit chips and testing of the interconnect wiring between integrated circuit chips. The test circuitry, disposed within the interposer substrate comprises semiconductor logic circuitry that electrically connects to the integrated circuit chips of the module. In the various multiplexer latch and shift register latch embodiments disclosed, active test circuitry within the interposer substrate is minimized and is essentially transparent to the integrated circuit chip designs incorporated in the MCM.

Multichip module with integrated test circuitry disposed within

The improved register file includes an array of storage cells arranged in columns and rows, each column having a pair of bit lines for writing into the cell. Each storage cell includes a flip-flop cell having a first storage node connected to a respective read line which is unique for that cell. A read address latch has an enabling input connected to the master clock signal which is the same master clock signal for the LSSD logic on the integrated circuit chip. The read address latch applies its decoded output to a multiplexer which selects those read lines coming from one of the rows of storage cells in the array, and applies those selected read lines to an output storage cell array. The output storage cell array is enabled by a slave clock signal which is the same slave clock signal employed in the LSSD logic on the same integrated circuit chip. The output storage cell array stores the data from the selected read lines out of the multiplexer. The multiplexer propagates the data signals output from the read lines and performs the selection during the delay period between the master clock signal and the slave clock signal. Thus, the circuit makes use of the dead time between the master clock signal and the slave clock signal which was heretofore wasted, in performing the selection of the read lines for latching in the output storage cell array. The feature of connecting separate read lines to each respective storage cell in the array allows the independent accessing of different register rows in the register file for reading and writing, during the same logic cycle defined by the interval for the occurrence of both the master and the slave clock pulses.

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Manassas, VA, United States of America

Thomas M Storey