Changxin Memory Technologies, Inc.

Thomas Jongwan Kwon

Lingguo Zhang

Lintao Zhang

Xiangui Zhou

Xu Liu

Some embodiments of the present application provide a memory forming method and a memory. The method includes: providing a substrate including at least word line structures and active regions, and bottom dielectric layers and bit line contact layers located on a top surface of the substrate, the bottom dielectric layer having bit line contact openings exposing the active regions in the substrate, and the bit line contact layers covering the bottom dielectric layers and filling the bit line contact openings; etching part of the bit line contact layers to form the bit line contact layers of different heights; forming conductive layers, top surfaces of the conductive layers being at the same height in a direction perpendicular to an extension direction of the word line structures; and the top surfaces of the conductive layers being at different heights in the extension direction of the word line structures; forming top dielectric layers.

Memory forming method and memory

A method for forming a memory device includes: providing a substrate including at least word line structures and active regions, and a bottom dielectric layer and bit line contact layers that are on a top surface of the substrate; part of the bit line contact layers are etched to form bit line contact layers at different heights; conducting layers are formed, top surfaces of the conducting layers being at different heights in a direction perpendicular to an extension direction of the word line structure, and the top surfaces of the conducting layers being at different heights in the extension direction of the word line structure; top dielectric layers are formed; and etching is performed to form separate bit line structures.

Method for forming memory and memory

The present disclosure provides a forming method of a memory and a memory. The method includes: providing a substrate, wherein the substrate includes at least word line structures and active areas, and a bottom dielectric layer and a bit line contact layer located on a top surface of the substrate, the bottom dielectric layer has bit line contact openings, the bit line contact openings expose the active areas in the substrate, and the bit line contact layer covers the bottom dielectric layer and fills the bit line contact openings; etching parts of the bit line contact layer, and forming first bit line contact layer with different heights; forming a conductive layer, a top surface of the conductive layer is located at different heights in a direction perpendicular to an extension direction of the word line structures.

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Hefei, China

Thomas Jongwan Kwon