Honeywell G.m.b.h.

Atmel Corporation

Richard K. Spielberger

Thomas J. Dunaway

James M. Poplett

Thomas J Dunaway

Richard K Spielberger

Lori A Dicks

Jerald M Loy

Deborah A Cullinan

James M Poplett

John C Wittenberger

Francis J Belcourt

Michael W Heinks

Richard K Speilberger

Luverne O Balgaard

An integrated circuit package for use in radiation environments includes a base for receiving an integrated circuit die and has a peripheral surface for receiving a lid. The lid has an inner surface facing the die that has a cladding of a low atomic number material to limit electron emission due to absorbed radiation.

IC package lid for dose enhancement protection

A process of providing a bond pad arrangement for use with a thermocompression wire bonder including a primary bond pad for connection of an integrated circuit during a production assembly process, and a secondary test bond pad contiguous with the primary bond pad for connection of a wire to the integrated circuit. Including performing a test sequence, and removing the wire from the secondary test bond pad.

Test and tear-away bond pad design

Method for testing bare semiconductor die which includes providing a test substrate with a die receiving surface and bond pads with conductive traces which extend away from the surface and are connected to leads that may be contacted with test probes. A vacuum source is applied to an aperture in the die receiving surface. Atmospheric pressure holds the die in place during the connection of thin wires. After connection, the die is held in place during testing by the thin wires.

Vacuum die bond for known good die assembly

A method of making a temporary connection to an unpackaged semiconductor die, removing the temporary connection and preparing the site of the temporary connection to receive a permanent connection.

Method for providing a test connection and a permanent connection site

A semiconductor package including a base having a chip receiving portion and a surrounding portion; a bridge having conductive strips extending over the chip and supported at the surrounding portion; wires connect the conductive strips to power and ground; and wires connect the conductive strips to chip area power and ground bonding pads. Decoupling capacitors may be mounted on the base.

Semiconductor package with a bridge for chip area connection

An integrated circuit package for use in radiation environments includes a base and a lid of insulative materials. The base has a recess for receiving a die and a seal ring located on the periphery. The lid has a central insulation portion and an outwardly extending flange which can be welded to the seal ring.

Semiconductor package with weldable ceramic lid

Disclosed is a composition and method for providing conductive electronic component high strength bonding. The composition comprises an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead. The method invention comprises providing a leadframe comprising at lest one of power, ground, and signal conductive elements; and preforming solder material onto one of the conductive elements, the solder bonding material having an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead.

Package to semiconductor chip active interconnect site method

A decoupling apparatus for a microcircuit provides for a custom capacitor to be placed directly on the passivated upper surface of the integrated circuit or alternatively to be placed directly under the integrated circuit. In another alternative, multiple standard chip capacitors are placed directly on the passivated upper surface and connected by wire bonds to metal bars also resting on the upper surface.

Direct microcircuit decoupling

A scratch reducing shadow mask for providing vapor deposition patterns of bonding metals onto a surface of a die. The shadow mask comprises a top surface and a bottom surface which define a plurality of vias for permitting vaporized bonding metals to pass through the mask. Mask bottom surface comprises a plurality of recessed regions to minimize the contact area of the mask with the die during the vapor deposition process.

Method of making a surface etched shadow mask

A method and apparatus for accurately positioning a semiconductor chip onto a die bond pad region of a semiconductor package. A frame is constructed for slidable contact with peripheral walls of a semiconductor package die cavity. A frame central aperture with a wide upper opening and a narrower lower opening guides a semiconductor chip dropped therethrough into a precise position in the die cavity.

Removable drop-through die bond frame

Disclosed is a stacked leadframe assembly for use with integrated circuit chips. The assembly comprises multiple leadframes arranged in stacked relation. Each leadframe comprises conductive elements and solder bumps for electrically and mechanically connecting selected conductive elements of the leadframes.

Stacked tab leadframe assembly

Method of die bonding semiconductor chip by using removable frame

Disclosed is a composition and method for providing conductive electronic component high strength bonding. The composition comprises an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead. The method invention comprises providing a leadframe comprising at least one of power, ground, and signal conductive elements; and preforming solder material onto one of the conductive elements, the solder bonding material having an effective amount of material which is less than 3% by weight of tin and greater than 97% by weight of lead.

Method of manufacturing a leadframe having conductive elements preformed

Disclosed is a semiconductor chip package comprising a plurality of programmable pads located on a surface of the package, each pad being adapted for interconnection with a semiconductor chip. The package also includes a plurality of signal connectors located on a surface of the package. In addition the package includes a plurality of signal connections, each signal connection providing an electrically conductive path between an individual programmable pad and a corresponding individual signal connector. A plurality of dedicated power or ground connectors are also located on a surface of the package. Conductive paths within the package provide apparatus for selectively connecting any programmable pad to a power or ground connector, any pad so connected also remaining connected to a corresponding signal connector.

Universal semiconductor chip package

Disclosed is a semiconductor chip package comprising a plurality of programmable pads located on a surface of the package, each pad being adapted for interconnection with a semiconductor chip. The package also includes a plurality of signal connectors located on a surface of the package. In addition, the package includes a plurality of signal connections, each signal connection providing an electrically conductive path between an individual programmable pad and a corresponding individual signal connector. A plurality of dedicated power or ground connectors are also located on a surface of the package. Conductive paths within the package provide apparatus for selectively connecting any programmable pad to a power or ground connector, any pad so connected also remaining connected to a corresponding signal connector.

Growing community of inventors

St. Louis Park, MN, United States of America

Thomas J Dunaway