Qualcomm Incorporated

Thomas Hua-Min Williams

Raj Kumar

Luis Chen

Khaja Ahmad Shaik

Smeeta Heggond

Keyurkumar Karsanbhai Kansagra

Matthew Chauncey Kusbit

Kaushik Baruah

Bed Raj Kandel

Katherine Zhang

Harini Siddaiah

Rinoj Thomas

JeongAh Park

An integrated circuit (IC) includes transistors formed in diffusion regions. In each transistor, a source and a drain extend in a first direction, and a gate is disposed on the diffusion region between the source and the drain. To reduce connection resistance through at least one of a source metal line and a drain metal line connected to the source and the drain of a transistor, one of the source metal line and the drain metal line extends farther than the other in the first direction to provide additional via landing area to support an interconnection via having reduced resistance without increasing side-to-side capacitance between the source and drain metal lines. Increasing the via landing area reduces connection resistance to the source and/or drain. Providing an extended source metal line and/or drain metal line allows a via landing area to be shifted in the first direction to reduce via capacitance.

Integrated circuits (ICs) employing multi-pattern metallization to optimize metal interconnect spacing for improved performance and related fabrication methods

A die includes fins extending in a first direction, a gate formed over the fins, the gate extending in a second direction that is perpendicular to the first direction, a first source/drain contact layer formed over the fins and extending in the second direction, and a second source/drain contact layer formed over the fins and extending in the second direction, wherein the first source/drain contact layer and the second source/drain contact layer are on opposite sides of the gate. The die also includes a first source/drain metal layer electrically coupled to the first source/drain contact layer, and a second source/drain metal layer electrically coupled to the second source/drain contact layer, wherein the first source/drain metal layer and the second source/drain metal layer do not overlap one or more of the fins.

Packed terminal transistors

An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.

Comb / fishbone metal stack

A MOS IC includes a first circuit including a first plurality of nMOS devices, a first p-tap cell, and a first dummy nMOS cell, and a second circuit including a first plurality of pMOS devices, a first dummy pMOS cell, and a first n-tap cell. The nMOS/pMOS devices are spaced apart in a first direction. The first p-tap cell and the first dummy nMOS cell are adjacent to each other in the first direction between the nMOS devices. The first dummy pMOS cell and the first n-tap cell are adjacent to each other in the first direction between the pMOS devices. The pMOS devices are adjacent to the nMOS devices in a second direction orthogonal to the first direction. The first p-tap cell/the first dummy pMOS cell and the first dummy nMOS cell/the first n-tap cell are respectively adjacent to each other in the second direction.

Dummy cell and tap cell layout structure

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Irvine, CA, United States of America

Thomas Hua-Min Williams