Infineon Technologies Ag

International Business Machines Corporation

Thomas Goebel

Erdem Kaltalioglu

Markus Schwerd

Johann Helneder

Andrea Mitchell

Werner Robl

Martin Seck

Sun-Oo Kim

Martina Hommel

Heinrich Körner

Wolfgang Klein

Holger Torwesten

Markus Naujok

Stefan Drexl

Jay William Strane

Heinrich Koerner

Rajeev Malik

Roy Charles Iggulden

Axel Brintzinger

Mihel Seitz

Gerald R Friese

Peter Wrschka

Padraic C Shafer

Sunoo Kim

Michael M Iwatake

Donna Diane Miura

Kwong Hon (Keith) Wong

Chet Dziobkowski

Heinrich Kôrner

A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels.

Passivated copper chip pads

A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.

Process for producing a multifunctional dielectric layer on a substrate

An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

Integrated circuit with capacitor and method for the production thereof

A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.

Integrated connection arrangements

Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials.

Method of forming support structures for semiconductor devices

An integrated circuit comprises a chip including a circuit area surrounded by a peripheral area, the peripheral area extending to an edge of the chip. The integrated circuitry is disposed within the circuit area. No active circuit is disposed within the peripheral area. A barrier is disposed within the peripheral area and surrounds the circuit area. The barrier includes a capacitor structure integrated therein.

Capacitor integrated in a structure surrounding a die

Support structures for semiconductor devices

In a method of fabricating a metallization structure during formation of a microelectronic device, the improvement of reducing metal shorts in blanket metal deposition layers later subjected to reactive ion etching, comprising:

Low Cu percentages for reducing shorts in AlCu lines

In a method of planarizing a semiconductor wafer, the improvement comprising polishing above metal interconnect lines to uniformly polish the topography of the wafer to a predetermined endpoint on the wafer sufficiently close above the metal interconnect lines, yet far enough away from the lines to prevent damage to the lines, comprising: a) filling gaps between metal interconnect lines of an inter metal dielectric in a wafer being formed, by depositing HDP fill on top of the metal interconnects, between the metal interconnects, and on the surface of a dielectric layer between the metal interconnects to create an HDP overfill; b) contacting the surface of HDP overfill of the processed semiconductor wafer from step a) with a fixed abrasive polishing pad; and c) relatively moving the wafer and the fixed abrasive polishing pad to affect a polishing rate sufficient to reach a predetermined endpoint and uniformly planar surface on the wafer sufficiently close above the metal interconnect lines and yet far enough away from the lines to prevent damage to the lines.

Integration scheme for metal gap fill, with fixed abrasive CMP

A method of forming a semiconductor device includes providing a semiconductor device including a conductor formed thereon. A dielectric layer is formed over the conductor and a recess is formed in the dielectric layer by removing a portion of the dielectric layer to expose at least a portion of the conductor. A first layer of aluminum is deposited over the top surface of the dielectric, along the sidewalls of the dielectric layer and over the exposed portion of the conductor without altering the temperature of the semiconductor device. A second layer of aluminum is deposited over the first layer of aluminum at a temperature greater than about 300&deg; C. A third layer of aluminum is deposited over the second layer of aluminum so as to completely fill the recess in the dielectric layer. The third layer of aluminum is slow deposited at a temperature greater than about 300&deg; C.

Three layer aluminum deposition process for high aspect ratio CL contacts

Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.

Method of eliminating back-end rerouting in ball grid array packaging

Growing community of inventors

Munich, Germany

Thomas Goebel