Zeevo, Inc.

Samsung Electronics Co., Ltd.

Broadcom Corporation

Thomas G McKay

Stephen Allott

Christopher Donald Nilson

Subhas Bothra

Ravi Jhota

Joseph Barrera

An RF MOS transistor having improved AC output conductance and AC output capacitance includes parallel interdigitated source and drain regions separated by channel regions and overlying gates. Grounded tap regions contacting an underlying well are placed contiguous to source regions and reduce distributed backgate resistance, lower backgate channel modulation, and lower output conductance.

Split source RF MOSFET device

Disclosed is a frequency conversion circuit with sideband suppression in which a first mixer receives an in-phase signal (IF ) and is driven by a local oscillator having an in-phase (0&deg;) oscillator signal (LO ), and produces two sideband signals (LO&plus;IF, LO&minus;IF). A second mixer receives a quadrature phase frequency signal (IF &plus;) and is driven by a local oscillator having a quadrature (180&deg;) oscillator signal (LO ), and produces two sideband signals (LO&plus;IF , LO&minus;IF ). One of the sidebands from the second mixer is 180&deg; out of phase with respect to the same sideband from the first mixer. A signal combiner then receives and combines the two sidebands from the first mixer and the two sidebands from the second mixer, the signal combiner suppressing one sideband and enhancing the other sideband. In preferred embodiments, the mixers comprise MOSFET transistors and the signal combiner comprises capacitive elements.

CMOS frequency conversion using dual mixers for sideband suppression

Disclosed is a CMOS transistor amplifier for small RF signals which operates in a Class AB mode. The serially connected P channel and N channel transistors of the CMOS transistor pair have DC bias voltages applied to the control gates, and the small input signal is capacitively coupled to the gates of the CMOS transistor pair. In a preferred embodiment, the DC voltage bias for the P channel transistor is derived from a second P channel transistor which is approximately identical to the first P channel transistor in structure with the second P channel transistor serially connected with the current source and the voltage at the gate/drain of the transistor resistively coupled to the gate of the first P channel transistor. Similarly, the second bias circuit comprises a second N channel transistor which is approximately identical in structure to the first N channel transistor with the second N channel transistor serially connected with a current source and the bias voltage taken at the gate/drain of the second N channel transistor. The bias voltage is then applied through resistive means to the gate of the first N channel transistor.

Efficient AC coupled CMOS RF amplifier

Embodiments of the present invention provide a seal ring which includes a plurality of cuts separating the seal ring into seal ring portions which are disposed adjacent to different circuits in the integrated circuit die. The cuts reduce the noise coupling among the different circuits through the seal ring. To further isolate the sensitive RF/analog circuits from the noise generated by the digital circuit, the seal ring may be electrically (for dc noise) isolated from the substrate. This is accomplished, for instance, by inserting a polysilicon layer and gate oxide between the seal ring and the substrate. In addition, an n-well/p-well capacitor may be formed in series with the gate oxide, for instance, by implanting an n-well below the polysilicon layer in a p-type substrate. In this way, the seal ring provides substantially reduced noise coupling among the circuits but still maintains an effective wall around the periphery of the die to protect the circuits against moisture and ionic contamination penetration.

Seal ring structure for IC containing integrated digital/RF/analog circuits and functions

An improved FET for use as a voltage-controlled resistor includes a p-type control gate and a high-resistance connection to receive a control signal. The bootstrap frequency for the device is much lower than the signal frequency so that the signal frequency is decoupled from the control voltage to reduce distortion.

Voltage-controlled resistor utilizing bootstrap gate FET

An MMIC includes I/O pads on the back side coupled to active circuit structures on the front side by standard through-the-substrate vias. The front side is covered by a passivation layer and the back side I/O pads facilitate testing utilizing standard wafer probing equipment. The back side I/O pads are formed utilizing standard MMIC process technology.

Growing community of inventors

Felton, CA, United States of America

Thomas G McKay