Lsi Logic Corporation

Lam Research Corporation

Thomas G Mallon

Nicholas F Pasch

Mark A Franklin

Wei-Jen Hsia

Chi-Yi Kao

Atsushi Shimoda

Ashok K Kapoor

Douglas W Young

Nicholas K Eib

Keith K Chao

Prabhakar Pati Tripathi

Ratan K Choudhury

Anthony S Meyer

Gauri C Das

Bradley Withers

Disclosed is the formation of additional lines, either dummy lines or active lines, in an electrically conductive pattern of lines to provide more uniform loading for either etching or chemical/mechanical polishing of a layer of electrically conductive material from which the pattern of lines is formed. Also disclosed is the use of additional or dummy vias to balance the loading during etching of the vias, as well as to provide stress relief for underlying metal in regions or areas having a low density of vias. Further disclosed is the use of a working grid on the integrated circuit structure to analyze the spacing of lines or vias for the above effects.

Method for adjusting the density of lines and contact openings across a

A semiconductor integrated circuit is made by a process including the formation on a surface of a semiconductor integrated circuit processing wafer of a layer of material applied to the wafer by plasma enhanced chemical vapor deposition (PECVD). The layer of material may include plural sub-layers, the thicknesses of which are additive to result in the thickness of the layer of material itself. The sub-layers of material may have non-uniform thicknesses across a dimension of the processing wafer because of compromises in the process which are necessary to control various parameters of the material layer other than its thickness. These non-uniformities of thickness of the sub-layers may be controlled to offset one another so that the resulting layer of material has a substantially uniform thickness across the dimension of the processing wafer. A method, and apparatus for practicing the method, are set forth along with an explanation of how particular geometric factors of electrodes used in the PECVD process affect the resulting thickness non-uniformities. The thickness non-uniformities of the sub-layers may also be largely abated by use of the invention in a predictive-corrective fashion. A similar predictive-corrective method and resulting apparatus is set forth for gas plasma etching of an existing layer of material on a semiconductor integrated circuit processing wafer.

Semiconductor integrated circuit processing wafer having a PECVD

A platen ring for use with a platen on a linear polisher, in which the platen ring is used to reduce fluctuation of the belt/pad assembly as it encounters the platen. The platen ring is disposed around the platen so that a fluctuation of the belt/pad assembly is dampened before the belt/pad assembly engages the platen. Reduction of the belt/pad fluctuation ensures a reduction in the within-wafer non-uniformity and provides for a more uniform polishing rate across the surface of the wafer.

Technique for improving within-wafer non-uniformity of material removal

A method is provided for the controlled formation of voids in integrated circuit doped glass dielectric films. The film can be formed of borophosphosilica glass (BPSG) or other types of doped glass. The method involves the steps of providing a substrate on which conductors are formed, depositing a first layer of doped glass to a thickness in a predetermined ratio to the size of the space between conductors, reflowing the first doped glass layer, applying one or more additional doped glass layers to make up for any shortfall in desired total doped glass thickness, and performing a high temperature densification to smooth each additional layer. The method provides for increased integrated circuit speed by controlled formation of voids which have a low dielectric constant and therefore reduce capacitance between adjacent conductors. The method can be performed using existing doped glass deposition and reflow equipment.

Method for the controlled formation of voids in doped glass dielectric

A polishing pad conditioner has a grid with an abrasive surface for conditioning a polishing pad. Opposite the abrasive side of the grid, there is a back surface, having at least one key way, which extends at least partially into the back surface. A grid holder has a number of keys equal to the number of key ways in the back surface of the grid. The grid holder keys engage the grid key ways, thereby eliminating slippage between the grid and the grid holder. A mechanized arm is attached to the grid holder, and imparts a rotational and translational motion to the grid holder. A magnet may be used as an attachment means between the grid and the grid holder. The key ways of the grid and the keys of the grid holder may be arranged such that the grid holder can only receive the grid with the back surface of the grid facing the grid holder.

Keyed end effector for CMP pad conditioner

Plasma enhanced chemical vapor reactor with shaped electrodes

A technique for mounting polishing pads to a platen in chemi-mechanical semiconductor wafer polishing apparatus is disclosed. A lower pad is mounted to the platen, and is trimmed to the size of the platen. An upper pad is mounted to the lower pad, and is sized so that an extreme outer edge portion of the upper pad extends beyond the trimmed outer edge of the lower pad. The outer edge portion of the upper pad is deformed downwardly, towards the lower pad. In this manner, polishing slurry is diverted from the pad-to-pad interface. Additionally, an integral annular lip can be formed on the front face of the upper pad, creating a reservoir for slurry to be retained on the face of the upper pad for enhancing residence time of the polishing slurry prior to the slurry washing over the face of the upper pad.

Techniques for assembling polishing pads for chemi-mechanical polishing

Techniques for assembling polishing pads for chemical-mechanical

An improved Faraday Cage is provided for use in reducing ion damage to semiconductor wafers during plasma etching. The improved Faraday Cage consists of a cylindrical metallic chamber having a cap at one or more ends. Semiconductor wafers are placed within the Cage and the Cage is suitably disposed within a plasma etcher. The caps substantially reduce the amount of harmful radiation which can enter the Cage and thereby ion damage to the wafers contained therein. The improved Faraday Cage can be conveniently integrated with a barrel-style plasma etcher by securing one of the Cage caps to the door of the plasma etcher such that opening and closing the door serves to disengage and engage one of the caps from the Cage.

Growing community of inventors

Santa Clara, CA, United States of America

Thomas G Mallon