International Business Machines Corporation

Globalfoundries Inc.

Thomas Edward Lombardi

Thomas Weiss

David L Questad

Son K Tran

Donald Merte

Michael A Gaynes

Frank Louis Pompeo

Edmund D Blackshear

Sri Muthuthamby Sri-Jayantha

Jeffrey Donald Gelorme

James L Speidell

Steven Paul Ostrander

Marie-Claude Paquet

Steve Ostrander

Gregg B Monjeau

Robert P Kuder, Ii

Daniel J Littrell

John Ulrich Knickerbocker

Charles Leon Arvin

Hilton T Toy

Benjamin V Fasano

Sudipta Kumar Ray

Shidong Li

Mario John Interrante

Jiantao Zheng

Marcus E Interrante

Paul Francis Fortier

Richard Stephen Graf

Lester W Herron

Krishna R Tunga

Rajneesh Kumar

William Edward Sablinski

Mark William Kapfhammer

David Justin West

Elaine Cyr

Roger Lam

Jeffrey P Gambino

Mukta G Farooq

Alfred Grill

David Clifford Long

Wolfgang Sauter

Christopher David Muzzy

Robert K Leidy

Govindarajan Natarajan

Mark Kenneth Hoffmeyer

Kamal Kumar Sikka

Jon Alfred Casey

Krishna Gandhi Sachdev

Roger Allan Quon

Steven Lorenz Wright

Mark J LaPlante

Thomas Anthony Wassick

Subhash Laxman Shinde

James N Humenik

H Bernhard Pogge

Mitchell S Cohen

William Francis Landers

Robert Anthony Rita

Donald Rene Wall

Richard Francis Indyk

Raymond A Jackson

Rao Venkateswara Vallabhaneni

David B Goland

Dinesh Gupta

Srinivasa S N Reddy

Scott Ira Langenthal

Robert J Sullivan

Bhupender Singh

Anton Nenadic

Joseph C Sorbello

David J Lewison

Vincent P Peterson

Richard A Shelleman

Takeshi Takamori

Hai Pham Longworth

James Robert Wylder

Alan Piciacchio

Catherine Dufort

Kevin Drummond

Stephanie Allard

Amy B Ostrander

Jasvir Singh Jaspal

Katharine G Frase

Piyas Bal Chowdhury

Eric Turcotte

Joseph Jacobi

A flip chip device and methods for fabrication are provided. An interconnect layer for a device include a plurality of solder bumps arranged within the interconnect layer. A first subset of the plurality of solder bumps has a first cross-sectional area, where the first subset is arranged along a first position at a first edge of the interconnect layer. A second subset of the plurality of solder bumps has a second cross-sectional area, where the second subset is arranged at a second position of the interconnect layer. A third subset of the plurality of solder bumps is arranged between the first position and the second position, where the third subset has a plurality of cross-sectional areas.

Electronic package with varying interconnects

An integrated circuit package structure is provided that includes a chip carrier substrate, at least one processor die provided on the chip carrier substrate, a plurality of lateral escape wiring lines connected to and extending away from the at least one processor die, and a plurality of chips at least partially surrounding the processor die, at least one of the chips overlapping with at least one of the lateral escape wiring lines in a plan view. An interconnect structure of the chips includes at least one vertical power feed structure that is configured and positioned not to intersect with the lateral escape wiring lines in the plan view.

Near tier decoupling capacitors

In some embodiments, connecting a component to a substrate by adhesion to an oxidized solder surface includes: forming one or more conductive solder connections between the component and one or more conductive portions of the substrate; adhering the component to an oxidized surface of a solder portion applied to the substrate.

Connecting a component to a substrate by adhesion to an oxidized solder surface

A structure with controlled capillary coverage is provided and includes a substrate including one or more first contacts, a component and adhesive. The component includes one or more second contacts and a rib disposed at a distance from each of the one or more second contacts. The component is disposed such that the one or more second contacts are communicative with the one or more first contacts and corresponding surfaces of the substrate and the rib face each other at a controlled gap height to define a fill-space. The adhesive is dispensed at a discrete point whereby the adhesive is drawn to fill the fill-space by capillary action.

Structure with controlled capillary coverage

Multiple integrated circuit (IC) devices are connected to a top side metallization surface of a multi IC device carrier. The carrier includes resin based substrate layers and associated wiring line layers. To reduce stain of the resin layers, especially in region(s) within the carrier between the IC devices, a stiffener or stiffeners are applied to the back side metallization (BSM) surface of the IC device carrier. The stiffener(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the resin layer(s), thereby mitigating the risk for cracks forming and expanding within the resin layers.

Mitigating cracking within integrated circuit (IC) device carrier

A method of managing thermal warpage of a laminate which includes: assembling a stiffener and an adhesive on the laminate, the stiffener being a material that has a higher modulus of elasticity than the laminate; applying a force to deform the laminate a predetermined amount; heating the laminate, stiffener and adhesive to a predetermined temperature at which the adhesive cures to bond the stiffener to the laminate; cooling the laminate, stiffener and adhesive to a temperature below the predetermined temperature, the laminate maintaining its deformed shape.

Managing thermal warpage of a laminate

An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.

Method and apparatus for strain relieving surface mount attached connectors

A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

Fixture to constrain laminate and method of assembly

The disclosure relates to semiconductor structures and, more particularly, to barrier structures for underfill blockout regions uses in phonotics chip packaging and methods of manufacture. The structure includes a substrate with a plurality of solder connections and at least one optical fiber interface disposed within at least one cavity of the substrate. The structure further includes a barrier structure formed about the cavity which is structured to prevent underfill material from degrading an optical coupling of the optical fiber.

Barrier structures for underfill blockout regions

A technique relates to forming a chip assembly. Top and bottom chip stack elements containing solder pads and a solder material are provided. Soluble standoffs are applied to the bottom chip stack element. The chip stack elements are aligned to bring the top solder pad in proximity to the bottom solder pad and the temperature is raised to a temperature above the melting temperature of the solder material to form a connected chip assembly. The connected chip assembly is cooled to re-solidify the solder material and soluble standoffs are removed from the connected chip assembly.

Selectively soluble standoffs for chip joining

A method including providing a laminate substrate, characterizing the laminate substrate for warpage characteristics, determining a horizontal plane distortion based on the warpage characteristics, and placing the laminate substrate into a fixture with an adjustment to correct the horizontal plane distortion, the adjustment being located in a center of the laminate substrate, wherein the adjustment contacts the laminate substrate. The method may further include fluxing the laminate substrate, placing a chip onto the laminate substrate, and placing the fixture into a reflow furnace to join the chip and the laminate substrate.

Method for shaping a laminate substrate

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Poughkeepsie, NY, United States of America

Thomas Edward Lombardi