Fairchild Semiconductor Corporation

Intersil Corporation

Harris Corporation

Thomas E Grebs

Rodney S Ridley

Gary M Dolny

Christopher Boguslaw Kocon

Nathan Lawrence Kraft

Joseph Andrew Yedinak

Dean E Probst

Steven Paul Sapp

Hamza Yilmaz

Daniel S Calafut

Bruce Douglas Marchant

Mark L Rinehimer

John L Benjamin

Joseph L Cumbo

Jason R Trost

Malcolm R Schuler

Ashok Challa

Jifa Hao

Louise E Skurkey

Raymond J Webb

Robert F Longenberger

Michael A Caravaggio

Terry L Fenstermacher

Daniel Marvin Kinzer

John M Neilson

Jeffrey P Spindler

Becky Losee

Peter H Wilson

Christopher L Rexer

Babak S Sani

Jeffrey Edward Lauffer

Rodney S Ridley, Sr

Rodney Sylvester Ridley, Sr

Mark L Rineheimer

Chris Gasser

Jayson S Preece

John Mytych

Adam Selsley

A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric.

Trench-gate field effect transistor

Charge balanced semiconductor devices with increased mobility structures and methods for making and using such devices are described. The semiconductor devices contain a substrate heavily doped with a dopant of a first conductivity type, a strained region containing a strain dopant in an upper portion of the substrate, an epitaxial layer being lightly doped with a dopant of a first or second conductivity type on the strained region, a trench formed in the epitaxial layer with the trench containing a MOSFET structure having a drift region overlapping the strained region, a source layer contacting an upper surface of the epitaxial layer and an upper surface of the MOSFET structure, and a drain contacting a bottom portion of the substrate. Since the drift region of the MOSFET structure is formed from the strained region in the substrate, the mobility of the drift region is improved and allows higher current capacity for the trench MOSFET devices. Other embodiments are described.

Charge balance semiconductor devices with increased mobility structures

In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.

Shielded gate field effect transistors

This document discusses, among other things, a semiconductor device including first and second conductive layers, the first conductive layer including a gate runner and a drain contact and the second conductive layer including a drain conductor, at least a portion of the drain conductor overlying at least a portion of the gate runner. A first surface of the semiconductor device can include a gate pad coupled to the gate runner and a drain pad coupled to the drain contact and the drain conductor.

Multi-level options for power MOSFETS

Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

Reduced process sensitivity of electrode-semiconductor rectifiers

A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches.

Method of forming shielded gate power transistor utilizing chemical mechanical planarization

A field effect transistor includes a gate trench extending into a semiconductor region. The gate trench has a recessed gate electrode disposed therein. A source region in the semiconductor region flanks each side of the gate trench. A conductive material fills an upper portion of the gate trench so as to make electrical contact with the source regions along upper sidewalls of the gate trench. The conductive material is insulated from the recessed gate electrode.

Structure and method for forming trench-gate field effect transistor with source plug

High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.

Trench MOS barrier schottky rectifier with a planar surface using CMP techniques

Disclosed are semiconductor devices with breakdown voltages that are more controlled and stable after repeated exposure to breakdown conditions than prior art devices. The disclosed devices can be used to provide secondary circuit functions not previously contemplated by the prior art.

Semiconductor devices with stable and controlled avalanche characteristics and methods of fabricating the same

A semiconductor power device includes a plurality of groups of stripe-shaped gate trenches extending in a silicon region over a substrate, and a plurality of stripe-shaped sinker trenches each extending between two adjacent groups of the plurality of groups of stripe-shaped gate trenches. The plurality of stripe-shaped sinker trenches extend from a top surface of the silicon region through the silicon region and terminate within the substrate. The plurality of stripe-shaped sinker trenches are lined with an insulator along the sinker trench sidewalls so that a conductive material filling each sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench.

Semiconductor power device having a top-side drain using a sinker trench

Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described. An exemplary device comprises a semiconductor region having a surface, a first area of the semiconductor region, a well region of a first conductivity type disposed in the semiconductor region and around the first area, and a plurality of trenches extending in a semiconductor region. Each trench haves a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area. Each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer.

Trench-shielded semiconductor device

A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities.

Methods of forming inter-poly dielectric (IPD) layers in power semiconductor devices

A method of forming a field effect transistor includes: forming a trench in a semiconductor region; forming a shield electrode in the trench; performing an angled sidewall implant of impurities of the first conductivity type to form a channel enhancement region adjacent the trench; forming a body region of a second conductivity type in the semiconductor region; and forming a source region of the first conductivity type in the body region, the source region and an interface between the body region and the semiconductor region defining a channel region therebetween, the channel region extending along the trench sidewall. The channel enhancement region partially extends into a lower portion of the channel region to thereby reduce a resistance of the channel region.

Method of forming trench-gate field effect transistors

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Mountain Top, PA, United States of America

Thomas E Grebs