Infineon Technologies Ag

Osram Opto Semiconductors Gmbh

Infineon Technologies Austria Ag

Thomas Bemmerl

Michael Bauer

Simon Jerebic

Edward Fuergut

Martin Gruber

Thorsten Meyer

Thorsten Scharf

Michael Stadler

Hermann Vilsmeier

Joachim Mahler

Frank Singer

Markus Pindl

Anton Prueckl

Chooi Mei Chong

Bernd Rakow

Markus Fink

Azlina Kassim

Edward Myers

Thomas Mende

Ralf Otremba

Horst Theuss

Bernd Waidhas

Xaver Schloegel

Rainald Sander

Gerald Ofner

Irmgard Escher-Poeppel

Ulrich Streppel

Bert Braune

Peter Strobel

Christian Stuempfl

Steffen Thiele

Wae Chet Yong

Horst Groeninger

Thai Kee Gan

Michael Juerss

Ke Yan Tean

Martin Richard Niessner

Wee Boon Tay

Stephan Preuss

Edward Fürgut

Holger Wörner

Nurfarena Othman

Bun Kian Tay

Herman Vilsmeier

Horst Gröninger

Kuok Wai Chan

Christoph Liebl

A method of fabricating a semiconductor device package includes: providing a die carrier; disposing at least one semiconductor die on the die carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier; electrically connecting the semiconductor die or another electrical device with an electrical connector; applying an encapsulant above the semiconductor die, the die carrier, and the electrical connector; and screwing a metallic drilling screw through the encapsulant so that an end of the drilling screw contacts the electrical connector.

Method for fabricating a semiconductor device package comprising a pin in the form of a drilling screw

An electronic device and method is disclosed. In one example, the electronic device includes a solderable surface and at least one surface opening arranged in the solderable surface. The electronic device further includes an encapsulation material, encapsulating at least one electronic component of the electronic device, and at least one vent opening arranged in an area of the surface opening and extending through the encapsulation material.

Electronic devices including vent openings and associated methods

The semiconductor device package comprises a die carrier, at least one semiconductor die disposed on the carrier, the semiconductor die comprising at least one contact pad on a main face remote from the carrier, an encapsulant disposed above the semiconductor die, an electrical connector electrically connected with the contact pad, a drilling screw screwed through the encapsulant and connected with the electrical connector.

Semiconductor device package comprising a pin in the form of a drilling screw

A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

Semiconductor device having a contact clip with a contact region having a convex shape and method for fabricating thereof

A clip, a semiconductor package, and a method are disclosed. In one example the clip includes a die attach portion having a first main face and a second main face opposite to the first main face, and at least one through-hole extending between the first and second main faces and including a curved transition from an inner wall of the at least one through-hole to the first main face.

Semiconductor package and clip with a die attach

A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, an encapsulant encapsulating at least part of the electronic component and at least part of the carrier and having a bottom side at a first vertical level. At least one lead is electrically coupled with the electronic component and comprising a first lead portion being encapsulated in the encapsulant and a second lead portion extending out of the encapsulant at the bottom side of the encapsulant. A functional structure at the bottom side extends up to a second vertical level different from the first vertical level.

Package with elevated lead and structure extending vertically from encapsulant bottom

Semiconductor device and method for fabricating a semiconductor device

A semiconductor package includes a die pad having a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile, wherein an upper section of the die pad laterally overhangs past a lower section of the die pad, a semiconductor die mounted on the die attach surface and having a first electrical terminal on an upper surface of the semiconductor die, and a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that a section of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.

Semiconductor package with space efficient lead and die pad design

A leadless package includes an at least partially electrically conductive carrier having a mounting section and a lead section, an electronic chip mounted on the mounting section, and an encapsulant at least partially encapsulating the electronic chip and partially encapsulating the carrier so that at least part of an interior sidewall of the lead section not forming part of an exterior sidewall of the package is exposed.

Encapsulated leadless package having an at least partially exposed interior sidewall of a chip carrier

A semiconductor device is disclosed. In one example, the semiconductor device comprises a first semiconductor die comprising a first surface, a second surface opposite to the first surface, and a contact pad disposed on the first surface, a further contact pad spaced apart from the semiconductor die, a clip comprising a first layer of a first metallic material and a second layer of a second metallic material different from the first metallic material, wherein the first layer of the clip is connected with the contact pad, and the second layer of the clip is connected with the further contact pad.

Semiconductor device comprising a composite material clip

A semiconductor device includes a first chip pad, a power semiconductor chip arranged on the first chip pad and including at least a first and a second power electrode, and a clip connected to the first power electrode. In this case, an integral part of the clip forms a shunt resistor and a first contact finger of the shunt resistor is embodied integrally with the clip.

Semiconductor device with integrated shunt resistor

A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.

Semiconductor package system

A leadframe, that is to be incorporated into a semiconductor housing is provided. The leadframe may include a first die pad, a second die pad and a plurality of contact pads. A lower surface of the contact pads and a lower surface of the first die pad are arranged in a first plane. An upper surface of the second die pad is arranged in a second plane distant from the first plane by an overall thickness of the semiconductor package.

Leadframe, semiconductor package including a leadframe and method for forming a semiconductor package

An electronic arrangement comprising: a carrier; at least one connecting area on the carrier; at least one electronic component, which is fixed at least on the connecting area by a contact material; a covering area, which surrounds the connecting area on the carrier; and at least one covered region covered by a covering material; wherein the covering area is highly reflective with a reflectivity of greater than 70%, exposed regions on the connecting area and on the contact material are covered with the covering material, and the covering material is colored by titanium dioxide particles in such a way that the titanium dioxide particles are provided in the covering material in a proportion between 25 percent and 70 percent by weight, such that the covering material is highly reflective with a reflectivity of greater than 70% to minimize optical contrast between the covering area and the covered region.

Electronic arrangement

An electronic arrangement () comprising a carrier (), on which at least one connecting area () is arranged. At least one electronic component () is fixed on the connecting area () by means of a contact material (). A covering area () surrounds the connecting area () on the carrier (). At least one covered region () is covered by a covering material (). The covering material () is designed in such a way that an optical contrast between the covering area () and the covered region () is minimized.

Electronic arrangement and method for producing an electronic arrangement

Growing community of inventors

Schwandorf, Germany

Thomas Bemmerl