Siltronic Ag

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Wacker Chemie Ag

Wacker Siltronic Gesellschaft Fur Halbleitermaterialien Ag

Wacker Siltronic Gesellschaft F&uuml;r Halbleiter Materialien Ag

Wacker Siltronic Gesellschaft F{dot Over (u)}r Halbleitermaterialien Ag

Thomas Altmann

Heinz Kraus

Anton Huber

Laszlo Fabry

Guido Wenski

Gerhard Heier

Wolfgang Winkler

Ernst Feuchtinger

Willibald Bernwinkler

Alexander Heilmaier

Wolfgang Siebert

Klaus Messmann

Johann Glas

Gunther Kann

Hans Peter Sendlinger

Martin Fürfanger

Ivo Croessmann

In the batch production of high purity polycrystalline silicon, in which a U-shaped silicon carrier body is fastened in an open deposition reactor, the deposition reactor is hermetically sealed, the U-shaped carrier body is heated electrical current, a silicon-containing reaction gas and hydrogen are introduced into the reactor through a supply line so that silicon from the reaction gas is deposited on the carrier body, the diameter of the carrier body increases and a waste gas formed is removed from the deposition reactor through a discharge line, and, after a desired diameter of the polysilicon rod is reached, deposition is terminated, the carrier body is cooled to room temperature, the reactor is opened, the carrier body is removed from the reactor and a second U-shaped silicon carrier body made of silicon is fastened in the deposition reactor, an inert gas is fed through the supply and discharge lines into the open reactor from at least the time when the reactor is opened to extract the first carrier body with deposited silicon, until at least the time when the reactor is closed in order to deposit silicon on the second carrier body.

Method and device for producing high purity polycrystalline silicon with a reduced dopant content

A semiconductor wafer with a front surface and a back surface and an epitaxial layer of semiconducting material deposited on the front surface. In the semiconductor wafer, the epitaxial layer has a maximum local flatness value SFQRof less than or equal to 0.13 &#x3bc;m and a maximum density of 0.14 scattered light centers per cm. The front surface of the semiconductor wafer, prior to the deposition of the epitaxial layer, has a surface roughness of 0.05 to 0.29 nm RMS, measured by AFM on a 1 &#x3bc;m&#xd7;1 &#x3bc;m reference area. Furthermore, there is a process for producing the semiconductor wafer. The process includes the following process steps: (a) as a single polishing step, simultaneous polishing of the front surface and of the back surface of the semiconductor wafer between rotating polishing plates while an alkaline polishing slurry is being supplied, the semiconductor wafer lying in a cutout of a carrier whose thickness is dimensioned to be 2 to 20 &#x3bc;m less than the thickness of the semiconductor wafer after the latter has been polished; (b) simultaneous treatment of the front surface and of the back surface of the semiconductor wafer between rotating polishing plates while a liquid containing at least one polyhydric alcohol having 2 to 6 carbon atoms is being supplied; (c) cleaning and drying of the semiconductor wafer; and (d) deposition of the epitaxial layer on the front surface of the semiconductor wafer produced in accordance with steps (a) to (c).

Epitaxially coated semiconductor wafer and process for producing it

A silicon semiconductor wafer with a diameter of greater than or equal to 200 mm and a polished front surface and a polished back surface and a maximum local flatness value SFQRof less than or equal to 0.13 &#x3bc;m, based on a surface grid of segments with a size of 26 mm&#xd7;8 mm on the front surface, wherein the maximum local height deviation P/V(10&#xd7;10)of the front surface from an ideal plane is less than or equal to 70 nm, based on sliding subregions with dimensions of 10 mm&#xd7;10 mm. There is also a process for producing a multiplicity of silicon semiconductor wafers by simultaneous double-side polishing between in each case one lower polishing plate and one upper polishing plate, which rotate, are parallel to one another and to which polishing cloth has been adhesively bonded, while a polishing agent, which contains abrasives or colloids, is being supplied, with at least 2 &#x3bc;m of silicon being removed, wherein a predetermined proportion of the semiconductor wafers is at least partially polished using a lower polishing pressure, and a further proportion of the semiconductor wafers is polished using a higher polishing pressure.

Double-sided polishing process for producing a multiplicity of silicon semiconductor wafers

A process is for material-removing machining, on both sides simultaneously, of semiconductor wafers having a front surface and a back surface, the semiconductor wafers resting in carriers which are set in rotation by means of an annular outer drive ring and an annular inner drive ring and being moved between two oppositely rotating working disks in a manner which can be described by means of in each case one path curve relative to the upper working disk and one path curve relative to the lower working disk, wherein the two path curves after six loops around the center have the appearance of still being open, and at each point have a radius of curvature which is at least as great as the radius of the inner drive ring.

Process for material-removing machining of both sides of semiconductor wafers

Double-side polishing process with reduced scratch rate and device for carrying out the process

A semiconductor wafer has a front surface and a back surface and flatness values based on partial areas of a surface grid on the front surface of the semiconductor wafer, which has a maximum local flatness value SFQR of less than or equal to 0.13 &mgr;m and individual SFQR values which in a peripheral area of the semiconductor wafer do not differ significantly from those in a central area of the semiconductor wafer. There is also a process for producing this semiconductor wafer, wherein the starting thickness of the semiconductor wafer is 20 to 200 &mgr;m greater than the thickness of the carrier and the semiconductor wafer is polished until the end thickness of the semiconductor wafer is 2 to 20 &mgr;m greater than the thickness of the carrier.

Semiconductor wafer with improved flatness, and process for producing the semiconductor wafer

A process for the double-side polishing of semiconductor wafers between two polishing plates which rotate in opposite directions and are covered with polishing cloth, so that at least 2 &mgr;m of semiconductor material is removed. The semiconductor wafers lay in plastic-lined cutouts in a set of a plurality of planar carriers which are made from steel and the mean thickness of which is 2 to 20 &mgr;m smaller than the mean thickness of the fully polished semiconductor wafers. The set comprises only those carriers whose difference in thickness is at most 5 &mgr;m, and each carrier belonging to the set has at least one unambiguous identification feature which assigns it to the set. An item of information contained in the identification feature is used in order for the plastic linings to be exchanged at fixed intervals and to ensure that the semiconductor wafers remain in the same order after the polishing as before the polishing. There is also a carrier which is suitable for carrying out the process.

Process for the double-side polishing of semiconductor wafers and carrier for carrying out the process

Growing community of inventors

Haiming, Germany

Thomas Altmann