Sperry Rand Corporation

Thomas A Pogemiller

Merton A Horne

A method and sense latch circuit are described for determining the memory retention characteristics of differentially sensed metal nitride oxide semiconductor field effect transistor (MNOS FET) memory cells and arrays made up of such cells. The method involves substitution of one differential comparator input with a known reference voltage (VR) for determining the analog voltage threshold levels of the memory cells. The sense latch circuit, which can be fabricated as an integrated circuit, is responsively coupled to control inputs so that it can be operated in either a read or memory retention interrogation mode. The determination of the analog threshold levels of each cell of an array at given times permits the determination of the array's memory window (i.e., memory retention characteristics).

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Burnsville, MN, United States of America

Thomas A Pogemiller