Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Advanced Micro Devices Corporation

Thilo Scheiper

Jan Hoentschel

Stefan Flachowsky

Sven Beyer

Uwe Griebenow

Andy C Wei

Peter Baars

Steven Langdon

Peter Javorka

Klaus Hempel

Shiang Yang Ong

Markus Lenski

Martin Trentzsch

Ralf Illgen

Andreas Kurz

Stefanie Steiner

Thorsten E Kammler

Thomas Werner

Rolf Stephan

Maciej Wiatr

Richard Carter

Ricardo Pablo Mikalo

Clemens Fitz

Kerstin Ruttloff

Carsten Grass

Stephan-Detlef Kronholz

Marco Lepper

Johannes F Groschopf

Robert Mulfinger

Vivien Schroeder

Roland Stejskal

Lithographic limitations on gate and induced channel length in MOSFETS are avoided by forming non-planar MOSFETS in a cavity extending into a semiconductor substrate. The gate insulator and channel region lie proximate a cavity sidewall having angle &#x3b1; preferably about &#x2267;90 degrees with respect to the semiconductor surface. The channel length depends on the bottom depth of the cavity and the depth from the surface of a source or drain region adjacent the cavity. The corresponding drain or source lies at the cavity bottom. The cavity sidewall extends therebetween. Neither depth is lithographic dependent. Very short channels can be consistently formed, providing improved performance and manufacturing yield. Source, drain and gate connections are brought to the same surface so that complex circuits can be readily constructed. The source and drain regions are preferably formed epitaxially and strain inducing materials can be used therein to improve channel carrier mobility.

Canyon gate transistor and methods for its fabrication

Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region.

Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process

A method of controlling temperature in a semiconductor device that includes a stacked device configuration is disclosed. The method includes providing a Peltier element having a metal-based heat sink formed above a first substrate of the stacked device configuration and a metal-based heat source formed above a second substrate of the stacked device configuration, and establishing a current flow through the Peltier element when the semiconductor device is in a specified operating phase.

Semiconductor device comprising a stacked die configuration including an integrated peltier element

Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.

Reduced threshold voltage-width dependency in transistors comprising high-K metal gate electrode structures

In sophisticated semiconductor devices, the contact structure may be formed on the basis of contact bars formed in a lower portion of an interlayer dielectric material, which may then be contacted by contact elements having reduced lateral dimensions so as to preserve a desired low overall fringing capacitance. The concept of contact bars of reduced height level may be efficiently combined with sophisticated replacement gate approaches.

Contact bars with reduced fringing capacitance in a semiconductor device

When forming sophisticated SOI devices, a substrate diode and a film diode are formed by using one and the same implantation mask for determining the well dopant concentration in the corresponding well regions. Consequently, during the further processing, the well dopant concentration of any transistor elements may be achieved independently from the well regions of the diode in the semiconductor layer.

SOI semiconductor device comprising a substrate diode and a film diode formed by using a common well implantation mask

Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.

Field effect transistors for a flash memory comprising a self-aligned charge storage region

Reduced threshold voltage-width dependency in transistors comprising high-k metal gate electrode structures

Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bounded by the first and second sidewall spacers. The method removes an upper portion of the first sidewall spacer and deposits a layer of metal in the trench and over a remaining portion of the first sidewall spacer to form a gate electrode and an interconnect.

Methods for fabricating integrated circuits having gate to active and gate to gate interconnects

Disclosed herein is a method of forming a semiconductor device. In one example, the method includes performing a first process operation to form a first etch stop layer above a first region of a semiconducting substrate where a first type of transistor device will be formed, and forming a first stress inducing layer at least above the first etch stop layer in the first region, wherein the first stress inducing layer is adapted to induce a stress in a channel region of the first type of transistor. The method further includes, after forming the first etch stop layer, performing a second process operation form a second etch stop layer above a second region of the substrate where a second type of transistor device will be formed, and forming a second stress inducing layer at least above the second etch stop layer in the second region, wherein the second stress inducing layer is adapted to induce a stress in a channel region of the second type of transistor. In one particular example, the first and second etch stop layers may have the same approximate thickness.

Method of forming contacts for devices with multiple stress liners

Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate and forming a plurality of spacers proximate the gate electrode structures, wherein the plurality of spacers comprises a first silicon nitride spacer positioned adjacent a sidewall of the gate electrode structure, a generally L-shaped silicon nitride spacer positioned adjacent the first silicon nitride spacer, and a silicon dioxide spacer positioned adjacent the generally L-shaped silicon nitride spacer.

Method of forming spacers that provide enhanced protection for gate electrode structures

A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, each including a SiOcap, forming extension regions at opposite sides of the first HKMG gate stack, forming a nitride liner and oxide spacers on each side of HKMG gate stack; forming a hardmask over the second HKMG gate stack; forming eSiGe at opposite sides of the first HKMG gate stack, removing the hardmask, forming a conformal liner and nitride spacers on the oxide spacers of each of the first and second HKMG gate stacks, and forming deep source/drain regions at opposite sides of the second HKMG gate stack.

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

A HKMG device with PMOS eSiGe source/drain regions is provided. Embodiments include forming first and second HKMG gate stacks on a substrate, forming a nitride liner and oxide spacers on each side of each HKMG gate stack, performing halo/extension implants at each side of each HKMG gate stack, forming an oxide liner and nitride spacers on the oxide spacers of each HKMG gate stack, forming deep source/drain regions at opposite sides of the second HKMG gate stack, forming an oxide hardmask over the second HKMG gate stack, forming embedded silicon germanium (eSiGe) at opposite sides of the first HKMG gate stack, and removing the oxide hardmask.

Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the surface topography of the isolation regions. To this end, a dielectric cap layer of superior etch resistivity is provided in combination with the conventional silicon dioxide material.

Superior integrity of high-k metal gate stacks by capping STI regions

Disclosed herein are various embodiments of an improved metal gate structure for semiconductor devices, such as transistors. In one example disclosed herein, a transistor has a gate structure consisting of a gate insulation layer positioned on a semiconducting substrate, a high-k insulation layer positioned on the gate insulation layer, a layer of titanium nitride positioned on the high-k insulation layer, a layer of aluminum positioned on the layer of titanium nitride and a layer of polysilicon positioned on the layer of aluminum.

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Dresden, Germany

Thilo Scheiper