Centre National De La Recherche Scientifique

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie Atomique

Université Grenoble Alpes

Université Joseph Fourier

Other

Institut Polytechnique De Grenoble

Cnrs

Centre National De La Recherche Scientifique-cnrs

Thierry Baron

Gabriel Molas

Karim Aissou

Pierre Ferret

Pascal Gentile

Mickaël Martin

Hubert Moriceau

Philippe Gilet

Emmanuel Augendre

Franck Fournel

Thomas Ernst

Julien Buckley

Jean-Michel Hartmann

Alexei Tchelnokov

Eric Jalaguier

Frédéric Mazen

Joël Eymery

Pierre Mur

Romain Gwoziecki

Fran&ccedil;ois Martin

Sebastien Fort

Marie-No&euml;lle Semeria

Virginie Loup

Marie-Noelle Semeria

Franck Bassani

François Martin

Bassem Salem

Marie-Noëlle Semeria

Hubert Eymery

Celine Ternon

No&euml;l Magnea

Maxime Legallais

Marc Plissonnier

Sami Halila

Redouane Borsali

Guillaume Gay

Pauline Serre

Sébastien Fort

Nol Magnea

A method for producing an aluminium nitride (AlN)-based layer on a structure with the basis of silicon (Si) or with the basis of a III-V material, may include several deposition cycles performed in a plasma reactor comprising a reaction chamber inside which is disposed a substrate having the structure. Each deposition cycle may include at least the following: deposition of aluminium-based species on an exposed surface of the structure, the deposition including at least one injection into the reaction chamber of an aluminium (Al)-based precursor; and nitridation of the exposed surface of the structure, the nitridation including at least one injection into the reaction chamber of a nitrogen (N)-based precursor and the formation in the reaction chamber of a nitrogen-based plasma. During the formation of the nitrogen-based plasma, a non-zero polarisation voltage Vmay be applied to the substrate.

Method for producing a layer of aluminum nitride (ALN) on a structure of silicon or III-V materials

A process for the hetero-integration of a semiconductor material of interest on a silicon substrate, includes a step of structuring the substrate which comprises a step of producing a growth mask on the surface of the silicon substrate, the growth mask comprising a plurality of masking patterns, two masking patterns being separated by a trench wherein the silicon substrate is exposed; a step of forming a two-dimensional buffer layer made of a 2D material, the buffer layer being free of side bonds on its free surface and being formed selectively on at least one silicon plane of [111] orientation in at least one trench, the step of forming a buffer layer being performed after the structuring step; a step of forming at least one layer of a semiconductor material of interest on the buffer layer. The semiconductor material of interest is preferably a IV-IV, III-V, II-VI semiconductor material and/or a 2D semiconductor material.

Process for the hetero-integration of a semiconductor material of interest on a silicon substrate

A process for epitaxying GaSe on a [111]-oriented silicon substrate, includes a step of selecting a [111]-oriented silicon substrate resulting from cutting a silicon bar in a miscut direction which is one of the three [11-2] crystallographic directions, the miscut angle (&#x3b1;) being smaller than or equal to 0.1&#xb0;, the obtained surface of the substrate forming a vicinal surface exhibiting a plurality of terraces and at least one step between two terraces; a passivation step consisting of depositing an atomic bilayer of gallium and of selenium on the vicinal surface of the silicon substrate so as to form a passivated vicinal surface made of silicon-gallium-selenium (Si&#x2014;Ga&#x2014;Se), said passivated vicinal surface exhibiting a plurality of passivated terraces and at least one passivated step between two passivated terraces; a step of forming a layer of two-dimensional GaSe by epitaxy on the passivated surface, said formation step comprising a step of nucleation from each passivated step and a step of lateral growth on the passivated terraces from the nuclei obtained in the nucleation step. A structure obtained by means of the epitaxying process is also provided.

Process for epitaxying gallium selenide on a [111]-oriented silicon substrate

A method for producing a network of nanostructures from at least one semiconductor material, including a step of forming nanostructures on the surface of a substrate, at least a part of the nanostructures having areas of contact between each other, comprising, in sequence and after the step of forming: a step of deoxidising the surface of the nanostructures and a step of reinforcing the bond between the nanostructures at the contact areas.

Polycrystalline semiconductor nanostructured material

A crystalline layer is produced from a crystalline substrate made from a first material on which a masking layer has previously been deposited; the masking layer containing at least one trench forming an access to the substrate, by:

Method for producing a microelectronic device

A material (M) includes a substrate one of the surfaces of which is covered with a layer based on a block copolymer having a block (B) consisting of a polysaccharide and to its uses for electronics, in order to prepare organic electroluminescent diodes (OLEDs) or organic photovoltaic cells (OPV) or for designing detection devices (nanobiosensors, biochips).

Thin films organized in nanodomains on the basis of copolymers having polysaccharide blocks for applications in nanotechnology

A method for fabricating patterns of III-V semiconductor material on a semiconductor substrate based on oriented silicon or germanium comprises: production of a growth mask on the surface of the substrate, defining masking patterns Miof width L, of height hwith a distance S between masking patterns; growth of patterns Miof III-V material between said masking patterns, such that said patterns exhibit a height h relative to the top plane of said masking patterns, said height h being at or above a critical minimum height h, the growth step comprising: determining growth rates vand vat right angles to the face of the III-V material, defining ratio R=v/v; determining the angle of dislocations &#x3b8; of the III-V material relative to the plane of the substrate; determining the critical minimum height hby the equation: with R being determined to be greater than tan(&#x3b8;).

Optimized method for fabricating patterns of III-V semiconductor material on a semiconductor substrate

A process for obtaining an array of nanodots () for microelectronic devices, characterized in that it comprises the following steps:

Process for obtaining an array of nanodots

A method for making a crossbar array of crossed conductive or semi-conductive access lines on a substrate, the crossbar array including on a crossbar array insulator, in a plane parallel to the substrate, a first level of lines including a plurality of first lines parallel with each other made of a conductive or semi-conductive material; on the first level of lines, a second level of lines including a plurality of second lines parallel with each other made of a conductive or semi-conductive material, the second lines being substantially perpendicular to the first lines. The method includes forming, on the substrate, a first cavity of substantially rectangular shape; forming a second cavity of substantially rectangular shape superimposed to the first cavity, the first and second cavities intersecting each other perpendicularly so as to form a resultant cavity.

Method for the realization of a crossbar array of crossed conductive or semi-conductive access lines

A process of making a microelectronic light-emitting device, including: a) growth on a metallic support of multiple wires based on one or more semi-conducting materials designed to emit radiant light, and b) formation of at least one electrical conducting zone of contact on at least one of the wires.

Method for making a light-emitting microelectronic device with semi-conducting nanowires formed on a metal substrate

A method for making a micro-electronic non-volatile memory device provided with transistors having gates placed side by side, the method comprising the steps of:

Fabrication of a memory with two self-aligned independent gates

Electrodes made from metallic material are formed on a layer of dielectric material. A bottom layer of at least one of the electrodes constitutes a catalyst material in direct contact with the layer of dielectric material. Nanowires are grown by means of the catalyst, between the electrodes, parallel to the layer of dielectric material. The nanowires connecting the two electrodes are then made from single-crystal semi-conductor material and in contact with the layer of dielectric material.

Method of growing, on a dielectric material, nanowires made of semi-conductor materials connecting two electrodes

A diblock copolymer layer comprising at least two polymers and having a lamellar structure perpendicularly to a substrate is deposited on a first gate insulator formed on the substrate. One of the polymers of the diblock copolymer layer is then eliminated to form parallel grooves in the copolymer layer. The grooves are filled by a first metallic or semi-conductor material and the rest of the copolymer layer is eliminated. A second dielectric material is deposited to form a second gate insulator. The second gate insulator of the floating gate then comprises an alternation of parallel first and second lines respectively of the first and second materials, the second material encapsulating the lines of the first material.

Method for producing a floating gate with an alternation of lines of first and second materials

The invention concerns a method for forming nanostructures of semi-conductor material on a substrate of dielectric material by chemical vapour deposition (CVD). Said method comprises the following steps: The invention further concerns nanostructures formed according to one of said methods as well as devices comprising said nanostructures.

Method for forming, by CVD, nanostructures of semi-conductor material of homogenous and controlled size on dielectric material

Method for automatic organization of microstructures or nanostructures and related device obtained

Growing community of inventors

Saint Egreve, France

Thierry Baron